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參數(shù)資料
| 型號： | TMP90C401 |
| 廠商： | Toshiba Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM，ROM，General Serial Interface,Multifunction Timer/Event Counter(高速、先進的 CMOS 8位微控制器（芯片集成了8位CPU,ROM，RAM，通用串行接口，多功能定時器/事件計數(shù)器）) |
| 中文描述： | 采用先進的CMOS高速8位微控制器，集成8位CPU，內(nèi)存，光盤，通用串行接口，多功能定時器/事件計數(shù)器（高速，先進的的CMOS 8位微控制器（芯片集成了8位的CPU，ROM和RAM內(nèi)存，通用串行接口，多功能定時器/事件計數(shù)器）） |
| 文件頁數(shù)： | 59/100頁 |
| 文件大小： | 2591K |
| 代理商： | TMP90C401 |
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TOSHIBA CORPORATION
59
TMP90C400/401
Output inversion by software
The timer flip-flops can be inverted by software regardless
of the timer operation. Writing “10” into
TFFCR <TFF1C1, 0> inverts TFF1
.
Initial setting of Timer Flip-flops
The timer flip-flops can be initialized to either “0” or “1”
without regard to the timer operation.
TFF1 is initialized to “0” by writing “00”, and to “1”
by writing “01” into TFFCR <TFF1C1,0>.
Note: Data from the timer flip-flops and timer registers
cannot be read.
(2)
16-bit Timer Mode
A pair of Timer 0 and Timer 1 or Timer 2 and Timer 3
can be used as one 16-bit interval timer.
Timers 2 and 3 do not provide output function, but
timer operations are the same with Timer 0 and 1. The
operation of a timer pair Timer 0 and Timer 1 is discussed.
Cascade connection of Timer 0 and Timer 1 to use
them as a 16-bit interval timer requires to set the
<T10M1,0> of the mode register TMOD to “0,1”.
By selecting the 16-bit timer mode, the overflow output
of Timer 0 is automatically selected as the input clock
to Timer 1, regardless of the set value of the clock
control register TCLK. The input clock to Timer 0 is
selected by TCLK. Table 3.6 (2) shows the relationship
between timer (interrupt) cycle and input clock selection.
Table 3.6 (2) 16-bit Timer (Interrupt) Cycle and Input Clock
Timer (interrupt) cycle
@fc = 10MHz
Resolution
Input clock to
Timer 0
0.8
12.8
204.8
μ
μ
s ~ 52.43ms
s ~ 838.86ms
μ
s ~ 13.425s
0.8
12.8
204.8
μ
μ
s
T1 (8/fc)
T16 (128/fc)
T256 (256/fc)
s
μ
s
The lower 8 bits of the timer (interrupt) cycle is set by
TREG0 and the upper eight bits of that is set by TREG1. Note
that TREG0 must be always set first (Writing data into TREG0
disables the comparator temporarily, which is restarted by
writing data into TREG1).
Example: To generate interrupts INTT1 at fc = 8MHz every
1 second, the timer registers TREG0 and
TREG1 should be set as follows:
As T16 (= 16
μ
s @ 8MHz) is selected as the
input clock, 1 sec/16
Therefore, TREG1 = F4H
TREG0 = 24H
μ
s = 62500 = F424H
The match signal is generated by Timer 0 comparator
each time the up-counter UC0 matches TREG0. In this case,
the up-counter UCO is not cleared, but the interrupt INTT0 is
generated.
Timer 1 comparator also generates the match signal each
timer the up-counter UC1 match TREG1. When the match
signal is generated simultaneously from comparators of Timer
0 and Timer 1, the up-counters UC0 and UC1 are cleared to
“0”, and the interrupt INTT1 is generated. If the timer flip-flop
inversion is enabled by the Timer Flip-flop control register, the
timer flip-flop TFF1 is inverted at the same time.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMP90C401F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C401N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C441 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| TMP90C441F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90C441N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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