參數(shù)資料
型號: TMP90C401
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM,ROM,General Serial Interface,Multifunction Timer/Event Counter(高速、先進的 CMOS 8位微控制器(芯片集成了8位CPU,ROM,RAM,通用串行接口,多功能定時器/事件計數(shù)器))
中文描述: 采用先進的CMOS高速8位微控制器,集成8位CPU,內(nèi)存,光盤,通用串行接口,多功能定時器/事件計數(shù)器(高速,先進的的CMOS 8位微控制器(芯片集成了8位的CPU,ROM和RAM內(nèi)存,通用串行接口,多功能定時器/事件計數(shù)器))
文件頁數(shù): 35/100頁
文件大?。?/td> 2591K
代理商: TMP90C401
TOSHIBA CORPORATION
35
TMP90C400/401
3.5.3 Port 2 (P20 ~ P27)
Port 2 includes a 6-bit (P20 ~ P25) general-purpose I/O port
and a 2-bit (P26, P27) output port (P2: memory address FF84H).
I/O functions are specified by the control register (P2CR: mem-
ory address FF85H) in bit basis.
A 6-bit I/O port has a programmable pull-up register
which functions when the output latch register is set to “1”. In
addition to I/O function P24 controls non-maskable interrupt
input pin (NMI), and P25 to P27 control external memory control.
These additional functions are specified by the function register
(P2FR: memory address FF86H). By resetting, all bits are
initialized to “1”, and the control/function register to “0”. As a
result, I/O port turns to the pull-up input port and the output
port outputs “1”.
P26 and P27 automatically function as memory control
pins (RD, WR) when accessing an external memory, and as
general-purpose ports when accessing an internal memory.
For accessing an external memory, the output latch registers
P26 (RD) and P27 (WR) should be kept at “1” which is the ini-
tial value after resetting.
Figure 3.5 (5). Port 2 (except P24)
相關(guān)PDF資料
PDF描述
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