參數(shù)資料
型號: TMP90C401
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM,ROM,General Serial Interface,Multifunction Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器(芯片集成了8位CPU,ROM,RAM,通用串行接口,多功能定時器/事件計數(shù)器))
中文描述: 采用先進(jìn)的CMOS高速8位微控制器,集成8位CPU,內(nèi)存,光盤,通用串行接口,多功能定時器/事件計數(shù)器(高速,先進(jìn)的的CMOS 8位微控制器(芯片集成了8位的CPU,ROM和RAM內(nèi)存,通用串行接口,多功能定時器/事件計數(shù)器))
文件頁數(shù): 63/100頁
文件大?。?/td> 2591K
代理商: TMP90C401
TOSHIBA CORPORATION
63
TMP90C400/401
The pulse width is normally changed by the interrupt
(INTT1) process routine in each cycle. However, when the
pulse width to be set (the value to be written in TREG0) is
small, trouble may occur, in that the timer counter exceeds the
value of TREG0 before the interrupt process routine is set.
Therefore, it is recommended to make the following decisions
in INTT0 and INTT1 interrupt processes.
INTT0 process routine: The value of TREG0 is rewritten
only when the value to be written
in TREG0 is smaller than the cur
rent value of TREG0.
INTT1 process routine: On the contrary to INTT0, TREG0
is written only when the value to
be written in TREG0 is larger than
the current value of TREG0.
TMP90C400 cannot read the content of TREG, so it is
necessary to buffer the content of TREG in a RAM (or the like)
for making the above judgement.
(4)
8-bit PWM (pulse width modulation) mode
This mode is only available for Timer1, and generates
8-bit resolution PWM.
PWM is output to TO1 pin (shared with P34).
Timer 0 can be used as 8-bit timers.
The inversion of the timer output occurs when the
up-counter (UC1) matches the set value of the timer register
TREG1, as well as when an overflow of 2
selected by TMOD <PWM01, 00>) occurred at the counter.
The up-counter UC1 is cleared by the occurrence of an
overflow of 2
- 1.
The following condition must be obtained when this PWM
mode is used:
n
- 1 (n = 6, 7 or 8
n
(Set value of timer register) < (set overflow value of 2
counter)
(Set value of timer register)
n
- 1
0
The PWM mode is shown in Figure 3.6 (12).
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