參數(shù)資料
型號: TMP90C401
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM,ROM,General Serial Interface,Multifunction Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器(芯片集成了8位CPU,ROM,RAM,通用串行接口,多功能定時器/事件計(jì)數(shù)器))
中文描述: 采用先進(jìn)的CMOS高速8位微控制器,集成8位CPU,內(nèi)存,光盤,通用串行接口,多功能定時器/事件計(jì)數(shù)器(高速,先進(jìn)的的CMOS 8位微控制器(芯片集成了8位的CPU,ROM和RAM內(nèi)存,通用串行接口,多功能定時器/事件計(jì)數(shù)器))
文件頁數(shù): 16/100頁
文件大?。?/td> 2591K
代理商: TMP90C401
16
TOSHIBA CORPORATION
TMP90C400/401
Table 3.3 (1) Interrupt Sources
Priority
order
Type
Interrupt source
Vector
Value
÷
8
Vector
Value
Start
address of
general-
purpose interrupt
processing
Start
address of
Micro DMA
processing
parameter
1
2
Non-
maskable
SWI instruction
NMI (Input from
NMI
pin)
02H
03H
10H
18H
0010H
0018H
3
4
5
6
7
8
9
10
Maskable
INTO (External input 0)
INTTO (Timer 0)
INTT1 (Timer 1)
INTT2 (Timer 2)
INTT3 (Timer 3)
INT1 (External input 1)
INTRX (End of serial receiving)
INTTX (End of serial transmission)
04H
05H
06H
07H
08H
09H
0AH
0BH
20H
28H
30H
38H
40H
48H
50H
58H
0020H
0028H
0030H
0038H
0040H
0048H
0050H
0058H
FF20H
FF28H
FF30H
FF38H
FF40H
FF48H
FF50H
FF58H
The “priority order” of Table 3.3 (1) shows the order of
the interrupt source to be acknowledge by the CPU when
more than one interrupt are requested simultaneously.
In interrupt of 4 and 5 orders are requested simultaneously,
for example, an interrupt of the “5th” priority is acknowledged
after a “4th” priority interrupt processing has been completed
by a RETI instruction. However, a lower priority interrupt can
be acknowledged immediately by executing an EI instruction
in a program that processes a higher priority interrupt.
The internal interrupt controller merely determines the priority
of the sources of interrupts to be acknowledged by the CPU
when more than one interrupt are requested at a time. It is,
therefore, unable to compare the priority of interrupt being
executed with the one being requested. To permit another
interrupt during a cetain iterrupt operation, set the interrupt
enabling flag for the source of the interrupt to be allowed, and
execute the EI command.
3.3.2 Micro DMA Processing
Figure 3.3 (3) is a flow chart of the micro DMA processing.
Parameters (addresses of source and destination, and transfer
mode) for the data transfer between memories are loaded by
the CPU from an address modified by an interrupt vector
value. After the data transfer between memories according to
these parameter, these parameters are updated and saved into
the original locations. The CPU then decrements the number of
transfers, and completes the micro DMA processing unless
the result is “0”.
If the number of transfer becomes “0”, the CPU proceeds
to the general-purpose interrupt processing described in
the previous item.
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