參數(shù)資料
型號(hào): TMP90C401
廠商: Toshiba Corporation
元件分類(lèi): 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit CPU,RAM,ROM,General Serial Interface,Multifunction Timer/Event Counter(高速、先進(jìn)的 CMOS 8位微控制器(芯片集成了8位CPU,ROM,RAM,通用串行接口,多功能定時(shí)器/事件計(jì)數(shù)器))
中文描述: 采用先進(jìn)的CMOS高速8位微控制器,集成8位CPU,內(nèi)存,光盤(pán),通用串行接口,多功能定時(shí)器/事件計(jì)數(shù)器(高速,先進(jìn)的的CMOS 8位微控制器(芯片集成了8位的CPU,ROM和RAM內(nèi)存,通用串行接口,多功能定時(shí)器/事件計(jì)數(shù)器))
文件頁(yè)數(shù): 69/100頁(yè)
文件大?。?/td> 2591K
代理商: TMP90C401
TOSHIBA CORPORATION
69
TMP90C400/401
Data received and transmitted are stored temporarily into
separate buffer registers to allow independent transmission
and receiving (full-duplex).
In the I/O interface mode, however, the data transfer is
half-duplex due to the single SCLK (serial clock) pin is used for
transmission and receiving.
Serial channel pins (RxD, SCL, TxD pins) are shared
among P35, P36 and P37, respectively. The pin function is
selected by P3CR and P3FR registers. P35 can be used as
RxD pin by setting P3CR <P35> to “0”. Also P36 and P37 can
be used as SCLK and TxD pins by setting P3CR6 <P37C,
P36C> to 11 and P3FR <SCLK, TXDC> to 11, respectively.
The receiving buffer register has a double-buffer structure
to prevent overruns. The one buffer receives the next frame
data while the other buffer stores the received data.
In the UART mode, a check function is added not to start
the receiving operation by error start bits due to noise. The
channel starts receiving data only when the start bit is
detected to be normal at least twice in three samplings.
When an request is issued to the CPU to transmit data
after the transmitting buffer becomes empty, or to read data
after the receiving buffer stores data, the interrupt INTTX or
INTRX occurs respectively, In receiving data, the flag SCCR
<OERR, FERR> is set when an overrun error, or framing error
occurs accordingly.
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