參數(shù)資料
型號(hào): TMS320C6414TBCLZ6
廠商: Texas Instruments
文件頁數(shù): 18/146頁
文件大?。?/td> 0K
描述: IC DSP FIXED POINT 532FC/CSP
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP,PCI,UTOPIA
時(shí)鐘速率: 600MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CCSP
供應(yīng)商設(shè)備封裝: 532-FC/CSP(23x23)
包裝: 管件
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
114
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY]
timing requirements for PCLK (see Figure 47)
NO.
600
720
850
1G
UNIT
MIN
MAX
1
tc(PCLK)
Cycle time, PCLK
30 (or 8P§)
ns
2
tw(PCLKH)
Pulse duration, PCLK high
11
ns
3
tw(PCLKL)
Pulse duration, PCLK low
11
ns
4
tsr(PCLK)
v/t slew rate, PCLK
1
4
V/ns
For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN.
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
§ Select the parameter value of 30 ns or 8P, whichever is greater.
PCLK
1
2
3
4
0.4 DVDD V MIN
Peak to Peak for
3.3V signaling
Figure 47. PCLK Timing
timing requirements for PCI reset (see Figure 48)
NO.
600
720
850
1G
UNIT
MIN
MAX
1
tw(PRST)
Pulse duration, PRST
1
ms
2
tsu(PCLKA-PRSTH)
Setup time, PCLK active before PRST high
100
s
PRST
PCLK
2
1
Figure 48. PCI Reset (PRST) Timing
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