參數(shù)資料
型號: TMS320C6414TBCLZ6
廠商: Texas Instruments
文件頁數(shù): 73/146頁
文件大?。?/td> 0K
描述: IC DSP FIXED POINT 532FC/CSP
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP,PCI,UTOPIA
時(shí)鐘速率: 600MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CCSP
供應(yīng)商設(shè)備封裝: 532-FC/CSP(23x23)
包裝: 管件
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
signal groups description
TRST
GP7/EXT_INT7
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Reset and
Interrupts
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
NMI
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
RESET
RSV
Clock/PLL
CLKIN
CLKMODE1
CLKMODE0
PLLV
EMU2
EMU3
EMU4
EMU5
RSV
GPIO
General-Purpose Input/Output (GPIO) Port
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
GP3
CLKOUT6/GP2
CLKOUT4/GP1
GP0
CLKOUT6/GP2
CLKOUT4/GP1
EMU6
EMU7
EMU8
EMU9
EMU10
GP15/PRST§
GP14/PCLK§
GP13/PINTA§
GP12/PGNT§
GP11/PREQ§
GP10/PCBE3§
GP9/PIDSEL§
CLKS2/GP8
These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2
clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be
properly enabled and configured. For more details, see the Device Configurations section of this data sheet.
These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or
GPIO as input-only.
RSV
EMU11
RSV
Peripheral
Control/Status
PCI_EN
MCBSP2_EN
For the C6415T and C6416T devices, these GPIO pins are muxed with the PCI peripheral pins. By default, these signals are set up
to no function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device
Configurations section of this data sheet. For the C6414T device, the GPIO peripheral pins are not muxed; the C6414T device does
not support the PCI peripheral.
§
Figure 3. CPU and Peripheral Signals
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