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參數(shù)資料
| 型號： | TMS320LC546 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP) |
| 中文描述： | 數(shù)字信號處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號處理器） |
| 文件頁數(shù)： | 16/107頁 |
| 文件大小： | 2149K |
| 代理商： | TMS320LC546 |
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TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
’C54x/’LC54x Signal Descriptions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE
INITIALIZATION, INTERRUPT AND RESET OPERATIONS (CONTINUED)
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
RS
I
Reset input. RS causes the DSP to terminate execution and forces the program counter to 0FF80h. When RS
is brought to a high level, execution begins at location 0FF80h of the program memory. RS affects various
registers and status bits.
MP/MC
I
Microprocessor/microcomputer mode-select pin. If active-low at reset (microcomputer mode), MP / MC causes
the internal program ROM to be mapped into the upper 28K words (’C541 and ’LC541) of program memory
space. In the microprocessor mode, off-chip memory and its corresponding addresses (instead of internal
program ROM) are accessed by the DSP.
CNT
I
I/O level select. For 5-V operation, all input and output voltage levels are TTL-compatible when CNT is pulled
down to a low level. For 3-V operation with CMOS-compatible I/O interface levels, CNT is pulled to a high level.
MULTIPROCESSING SIGNALS
BIO
I
Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor executes
the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
XF
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by RSBX XF instruction or by loading the ST1 status register. XF is used for signaling other processors in
multiprocessor configurations or as a general-purpose output pin. XF goes into the high-impedance state when
OFF is low, and is set high at reset.
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
communicating to a particular external space. Active period corresponds to valid address information. Placed into
a high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state when EMU1/OFF
is low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data
or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the high-impedance
state when OFF is low.
READY
I
Data-ready input. READY indicates that an external device is prepared for a bus transaction to be completed.
If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready-detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device and is normally
high (in read mode), unless asserted low when the DSP performs a write operation. Placed in the high-impedance
state in hold mode, R/W also goes into the high-impedance state when EMU1/OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an I/O
device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state when
EMU1/OFF is low.
HOLD
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the ’C54x, these lines go into high-impedance state.
HOLDA
O/Z
Hold acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that
the address, data, and control lines are in a high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when EMU1/OFF is low.
MSC
O/Z
Microstate complete signal. MSC goes low when the last wait state of two or more internal software wait states
programmed are executed. If connected to the READY line, MSC forces one external wait state after the last
internal wait state has been completed. MSC also goes into the high-impedance state when EMU1/OFF is low.
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus and goes into the high-impedance state when EMU1/OFF is low.
I = Input, O = Output, Z = High impedance
A
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