參數(shù)資料
型號: TMS320LC546
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(20/25ns指令周期, 高性能,大并行度,特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP)
中文描述: 數(shù)字信號處理器(20/25ns指令周期,高性能,大并行度,特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號處理器)
文件頁數(shù): 29/107頁
文件大?。?/td> 2149K
代理商: TMS320LC546
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
extended program memory (’LC548 only) (continued)
Six new instructions for addressing extended program memory space:
FB[D] — Far branch
FBACC[D] — Far branch to the location specified by the value in accumulator A or accumulator B
FCALA[D] — Far call to the location specified by the value in accumulator A or accumulator B
FCALL[D] — Far call
FRET[D] — Far return
FRETE[D] — Far return with interrupts enabled
Two ’54x instructions are extended to use the 23 bits in the ’LC548 device:
READA — Read program memory addressed by accumulator A and store in data memory
WRITA — Write data to program memory addressed by accumulator A
For more information on these six new instructions and the two extended instructions, refer to the instruction
set summary table in this data sheet and to the TMS320C54x DSP Reference Set, Volume 2, Mnemonic
Instruction Set literature number SPRU172. And for more information on extended program memory, refer to
the TMS320C54x DSP Reference Set, Volume 1, CPU and Peripherals literature number SPRU131.
data memory
The data memory space on the ’C54x/’LC54x device addresses contains up to 64K of 16-bit words. The
’C54x/’LC54x devices automatically access the on-chip RAM when addressing within its bounds. When an
address is generated outside the RAM bounds, the device automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the CALU
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
on-chip peripherals
All the ’C54x/’LC54x devices have the same CPU structure; however, they have different on-chip peripherals
connected to their CPUs. The on-chip peripheral options provided are:
Software-programmable wait-state generator
Programmable bank switching
Parallel I/O ports
Serial ports (standard, TDM, and BSP)
A hardware timer
A clock generator
software-programmable wait-state generators
Software-programmable wait-state generators can be used to extend external bus cycles up to seven machine
cycles to interface with slower off-chip memory and I/O devices. The software wait-state generators are
incorporated without any external hardware. For off-chip memory access, a number of wait states can be
specified for every 32K-word block of program and data memory space, and for one 64K-word block of I/O
space within the software wait-state (SWWSR) register.
A
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