參數(shù)資料
型號(hào)： TMS320LC546
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP)
中文描述： 數(shù)字信號(hào)處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號(hào)處理器）
文件頁(yè)數(shù)： 19/107頁(yè)
文件大?。?/td> 2149K
代理商： TMS320LC546
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
’C54x/’LC54x Signal Descriptions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE
IEEE1149.1 TEST PINS (CONTINUED)
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when EMU1/OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pullup device.
EMU0
I/O/Z
Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF
condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined
as input/output by way of IEEE standard 1149.1 scan system.
EMU1/OFF
I/O/Z
Emulator interrupt 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to
or from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When
TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output
drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not
for multiprocessing applications). Therefore, for the OFF condition, the following conditions apply:
TRST = low,
EMU0 = high
EMU1/OFF = low
DEVICE TEST PIN
TEST1
I = Input, O = Output, Z = High impedance
I
Test1 – Reserved for internal use only (’LC548 only).
This pin must not be connected (NC).
architecture
The ’C54x/’LC54x DSPs use an advanced, modified Harvard architecture that maximizes processing power
by maintaining three separate bus structures for data memory and one for program memory. Separate program
and data spaces allow simultaneous access to program instructions and data, providing a high degree of
parallelism. For example, two read and one write operations can be performed in a single cycle. Instructions
with parallel store and application-specific instructions fully utilize this architecture. In addition, data can be
transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the
’C54x/’LC54x include the control mechanisms to manage interrupts, repeated operations, and function calls.
The functional block diagram includes the principal blocks and bus structure in the ’C54x/’LC54x devices.
A
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參數(shù)描述
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