參數(shù)資料
型號(hào): TMS320LC546
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors(20/25ns指令周期, 高性能,大并行度,特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP)
中文描述: 數(shù)字信號(hào)處理器(20/25ns指令周期,高性能,大并行度,特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號(hào)處理器)
文件頁(yè)數(shù): 63/107頁(yè)
文件大小: 2149K
代理商: TMS320LC546
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external divide-by-two clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected, CLKMD1 and CLKMD2 set low, and CLKMD3 set high. This external frequency is divided by two
to generate the internal machine cycle.
The external frequency injected must conform to specifications listed in the timing requirements table.
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
] (see Figure 11
and Figure 12, and the recommended operating conditions table
)
PARAMETER
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
tc(CO)
Cycle time, CLKOUT
25
2tc(CI)
20
2tc(CI)
15
2tc(CI)
ns
td(CIH-CO)
Delay time, X2/CLKIN high to
CLKOUT high/low
6
12
18
6
12
18
6
12
18
ns
tf(CO)
tr(CO)
tw(COL)
tw(COH)
Will be defined after characterization
This device utilizes a fully static design and therefore can operate with tc(CI) approaching
. The device is characterized at frequencies
approaching 0 Hz but is tested at a minimum of 3.35 MHz to meet device test time requirements.
Fall time, CLKOUT
2
2
2
ns
Rise time, CLKOUT
2
2
2
ns
Pulse duration, CLKOUT low
H–4
H–2
H
H–4
H–2
H
H–4
H–2
H
ns
Pulse duration, CLKOUT high
H–4
H–2
H
H–4
H–2
H
H–4
H–2
H
ns
timing requirements over recommended operating conditions (see Figure 12)
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tc(CI)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
§This device utilizes a fully static design and therefore can operate with tc(CI) approaching
. The device is characterized at frequencies
approaching 0 Hz but is tested at a minimum of 6.7 MHz to meet device test time requirements.
Values derived from characterization data and not tested
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
Rise time, X2/CLKIN
12.5
§
10
§
7.5
§
ns
4
4
4
ns
4
§
4
§
4
§
ns
Pulse duration, X2/CLKIN low
3
3
3
ns
Pulse duration, X2/CLKIN high
3
§
3
§
3
§
ns
tr(CO)
tf(CO)
tw(COH)
CLKOUT
X2/CLKIN
tw(COL)
td(CIH–CO)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
tc(CO)
tc(CI)
Figure 12. External Divide-by-Two Clock Timing
A
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