參數(shù)資料
型號： TMS320LC546
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實現(xiàn)多種復雜算法及應用的DSP)
中文描述： 數(shù)字信號處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實現(xiàn)多種復雜算法及應用的數(shù)字信號處理器）
文件頁數(shù)： 93/107頁
文件大?。?/td> 2149K
代理商： TMS320LC546
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
90
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial-port receive timing in TDM mode
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
c(CO)
] (’542/’543 only) (see Figure 36)
’542
’543
UNIT
MIN
MAX
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
tsu(TD-TCL)
th(TCH-TD)
th(TCL-TD)
tsu(TF-TCH)
th(TCH-TF)
Values assured by design and are not tested
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching nfinity. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
§TFRM timing and waveforms shown in Figure 36 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 37.
Cycle time, serial-port clock
8H
ns
Fall time, serial-port clock
6
ns
Rise time, serial-port clock
6
ns
Pulse duration, serial-port clock low/high
4H
ns
Setup time, TDAT/TADD before TCLK falling edge
–(3H–9)
ns
Hold time, TDAT/TADD after TCLK rising edge, tw(SCKL) < 5H
Hold time, TDAT/TADD after TCLK falling edge, tw(SCKL) > 5H
Setup time, TFRM before TCLK rising edge§
Hold time, TFRM after TCLK rising edge§
0
ns
5H+5
ns
10
ns
10
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
c(CO)
] (all other ’C54x/’LC54x devices) (see Figure 36)
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN
MAX
MIN
MAX
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
tsu(TD-TCH)
th(TCH-TD)
tsu(TF-TCH)
th(TCH-TF)
Values assured by design and are not tested
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching nfinity. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
§TFRM timing and waveforms shown in Figure 36 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 37.
Cycle time, serial-port clock
8H
8H
ns
Fall time, serial-port clock
6
6
ns
Rise time, serial-port clock
6
6
ns
Pulse duration, serial-port clock low/high
4H
4H
ns
Setup time, TDAT/TADD before TCLK rising edge
25
10
ns
Hold time, TDAT/TADD after TCLK rising edge
Setup time, TFRM before TCLK rising edge§
Hold time, TFRM after TCLK rising edge§
– 6
0
ns
10
10
ns
10
10
ns
A
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