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Device Overview
2.1 Device Characteristics
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 2-1
, provides an overview of the TMS320DM6437 DSP. The tables show significant features of the
DM6437 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the
package type with pin count.
Table 2-1. Characteristics of the DM6437 Processor
HARDWARE FEATURES
DDR2 Memory Controller
DM6437
(16-/32-bit bus width) [1.8 V I/O]
Asynchronous (8-bit bus width),
RAM, Flash, (8-bit NOR
or
8-bit NAND)
1 (64 independent channels, 8 QDMA channels)
2 64-bit General Purpose
(configurable as 2 64-bit
or
4 32-bit)
1 64-bit Watch Dog
2 (one with RTS and CTS flow control)
1 (Master/Slave)
2
1 (4 serailizers)
Asynchronous EMIF [EMIFA]
EDMA3
Timers
UARTs
I2C
McBSPs
McASP
10/100 Ethernet MAC (EMAC) with
Management Data Input/Output (MDIO)
VLYNQ
General-Purpose Input/Output Port (GPIO)
PWM
HPI (16-bit)
PCI (32-bit), [33-MHz]
Peripherals
Not all peripherals pins
are available at the same
time (For more detail, see
the Device Configurations
section).
1
1
Up to 111 pins
3 outputs
1
1
1 Input (VPFE)
1 Output (VPBE)
1
240KB RAM, 64KB ROM
Configurable Video Ports
HECC
Size (Bytes)
32K-Byte (32KB) L1 Program (L1P) RAM/Cache
(Cache up to 32KB)
80KB L1 Data (L1D) RAM/Cache (Cache up to 32KB)
128KB Unified Mapped RAM/Cache (L2)
64KB Boot ROM
On-Chip Memory
Organization
Revision ID Register (MM_REVID.[15:0])
(address location: 0x0181 2000)
Control Status Register (CSR.[31:16])
JTAGID register
(address location: 0x01C4 0028)
MHz
See the
TMS320DM6437/35/33/31 Digital Media
Processor (DMP) [Silicon Revisions 1.1 and 1.0]
Silicon Errata
(literature number
SPRZ250
).
MegaModule Rev ID
CPU ID + CPU Rev ID
See
Section 6.24.1
,
JTAG ID (JTAGID) Register
Description(s)
400, 500, 600
2.5 ns (-400)
2 ns (-500)
1.67 ns (-600)
1.2 V (-600, -500, -400), 1.05 V (-400)
1.8 V, 3.3 V
JTAG BSDL_ID
CPU Frequency
Cycle Time
ns
Core (V)
I/O (V)
MXI/CLKIN frequency multiplier
(27 MHz reference)
16 x 16 mm, 0.8 mm pitch
23 x 23 mm, 1.0 mm pitch
μ
m
Voltage
PLL Options
x1 (Bypass), x14 to x 30
361-Pin BGA (ZWT)
376-Pin BGA (ZDU)
0.09
μ
m
BGA Package(s)
Process Technology
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Device Overview
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