
www.ti.com
P
3.2 Power Considerations
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
The DM6437 provides several means of managing power consumption.
As described in the
Section 6.3.4
,
DM6437 Power and Clock Domains
, the DM6437 has one single power
domain—the “Always On” power domain. Within this power domain, the DM6437 utilizes local clock gating
via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the PSC, see
Section 6.3.5
,
Power and Sleep Controller (PSC)
and the
TMS320DM643x DMP DSP Subsystem
Reference Guide (literature number
SPRU978
).
Some of the DM6437 peripherals support additional power saving features. For more details on power
saving
features
supported,
see
the
peripheral-specific
TMS320DM643x DMP Peripherals Overview
Reference Guide (literature number
SPRU983
).
reference
guides
[listed/linked
in
the
Most DM6437 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN
register in the System Module (see
Figure 3-1
) is used to selectively power down unused 3.3-V I/O pins.
For independent control, the 3.3-V I/Os are separated into functional groups—most of which are named
according to the pin multiplexing groups (see
Table 3-2
). For these I/O groups, only the I/O buffers needed
for Host/EMIFA Boot or Power-Up Operations are powered up by default (CLKOUT Block, EMIFA/VPSS
Block, Host Block, PCI Data Block, and GPIO Block).
Note:
To save power, all other I/O buffers are powered down by default. Before using these pins, the user
must
program the VDD3P3V_PWDN register to power up the corresponding I/O buffers.
For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see
Section 3.7.3.1
,
Multiplexed Pins on DM6437
.
Note:
The VDD3P3V_PWDN register
only
controls the power to the I/O buffers. The Power and Sleep
Controller (PSC) determines the clock/power state of the peripheral.
31
16
RESERVED
R-0000 0000 0000 0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
PCIDAT
EMBK3
UR0FC
UR0DAT
TIMER1
TIMER0
SP
PWM1
GPIO
HOST
EMBK2
EMBK1
EMBK0
CLKOUT
R-00
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Figure 3-1. VDD3P3V_PWDN Register
Submit Documentation Feedback
Device Configurations
77