
www.ti.com
P
5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted)
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
High-level output voltage (3.3V I/O except
PCI-capable and I2C pins)
DV
DD33
= MIN, I
OH
= MAX
2.4
V
V
OH
High-level output voltage (3.3V I/O
PCI-capable pins)
I
OH
= -0.5 mA, DV
DD33
= 3.3 V
0.9DV
DD33(2)
V
Low-level output voltage (3.3V I/O except
PCI-capable and I2C pins)
DV
DD33
= MIN, I
OL
= MAX
0.4
V
V
OL
Low-level output voltage (3.3V I/O
PCI-capable pins)
I
OH
= 1.5 mA, DV
DD33
= 3.3 V
0.1DV
DD33(2)
V
Low-level output voltage (3.3V I/O I2C pins) I
O
= 3 mA
0
0.4
V
V
= V
SS
to DV
DD33
without internal
resistor
±
10
μ
A
Input current [DC] (except I2C and PCI
capable pins)
V
= V
SS
to DV
DD33
with internal pullup
resistor
(4)
50
100
250
μ
A
V
= V
to DV
with internal
pulldown resistor
(4)
–250
–100
–50
μ
A
I
I(3)
Input current [DC] (I2C)
V
I
= V
SS
to DV
DD33
0 < V
I
< DV
DD33
= 3.3 V without internal
resistor
±
10
μ
A
±
10
μ
A
0 < V
< DV
= 3.3 V with internal
pullup resistor
(4)
Input current (PCI capable pins) [DC]
(5)
50
190
μ
A
0 < V
< DV
= 3.3 V with internal
pulldown resistor
(4)
–190
–50
μ
A
CLK_OUT0/PWM2/GPIO[84] and
VLYNQ_CLOCK/PCICLK/GP[57]
8
mA
DDR2
–13.4
mA
I
OH
High-level output current [DC]
PCI-capable pins
–0.5
(2)
mA
All other peripherals
4
mA
CLK_OUT0/PWM2/GPIO[84] and
VLYNQ_CLOCK/PCICLK/GP[57]
8
mA
DDR2
13.4
mA
I
OL
Low-level output current [DC]
PCI-capable pins
1.5
(2)
mA
All other peripherals
4
mA
V
= DV
DD33
or V
SS
; internal pull
disabled
±
20
μ
A
I
OZ(6)
I/O Off-state output current
V
= DV
DD33
or V
SS
; internal pull
enabled
±
100
μ
A
CV
DD
= 1.2 V, DSP clock = 600 MHz
CV
DD
= 1.2 V, DSP clock = 500 MHz
CV
DD
= 1.2 V, DSP clock = 400 MHz
CV
DD
= 1.05 V, DSP clock = 400 MHz
DV
DD
= 3.3 V, DSP clock = 600 MHz
DV
DD
= 3.3 V, DSP clock = 500 MHz
DV
DD
= 3.3 V, DSP clock = 400 MHz
TBD
mA
TBD
mA
I
CDD
Core (CV
DD
, V
DDA_1P1V
) supply current
(7)
TBD
mA
TBD
mA
TBD
mA
I
DDD
3.3V I/O (DV
DD33
) supply current
(7)
TBD
mA
TBD
mA
(1)
(2)
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
These rated numbers are from the
PCI Local Bus Specification Revision 2.3
. The DC specifications and AC specifications are defined in
Table 4-3 (DC Specifications for 3.3V Signaling) and Table 4-4 (AC Specifications for 3.3V Signaling), respectively.
I
applies to input-only pins and bi-directional pins. For input-only pins, I
indicates the input leakage current. For bi-directional pins, I
I
indicates the input leakage current and off-state (Hi-Z) output leakage current.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
I
applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
Measured under the following conditions: 60% DSP CPU utilization; DDR2 Memory Controller at 50% utilization (135 MHz), 50% writes,
32 bits, 50% bit switching; 2-MHz McBSP at 100% utilization; Timer0 at 100% utilization. At room temperature (25
°
C) for typical process
devices. The actual current draw varies across manufacturing processes and is highly application-dependent. For more details on core
and I/O activity, as well as information relevant to board power supply design, see the
TMS320DM643x Power Consumption Summary
Application Report (literature number TBD).
(3)
(4)
(5)
(6)
(7)
Device Operating Conditions
164
Submit Documentation Feedback