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TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 2-16. EMAC and MDIO Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
EMAC
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Enable output MTXEN.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Clock input MTXCLK.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Collision Detect input MCOL.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Data 3 output MTXD3.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Data 2 output MTXD2.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Data 1 output MTXD1.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Transmit Data 0 output MTXD0.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Clock input MRXCLK.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Data Valid input MRXDV.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Error input MRXER.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Carrier Sense input MCRS.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Data 3 input MRXD3.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Data 2 input MRXD2.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive data 1 input MRXD1.
This pin is multiplexed between HPI, Ethernet MAC (EMAC), PCI,
and GPIO.
In Ethernet MAC mode, it is Receive Data 0 input MRXD0.
MDIO
This pin is multiplexed between HPI, MDIO, PCI, and GPIO.
In Ethernet MAC mode, it is Management Data Clock output
MDCLK.
This pin is multiplexed between HPI, MDIO, PCI, and GPIO.
In Ethernet MAC mode, it is Management Data I/O MDIO
(I/O/Z)
.
HCNTL1/MTXEN/
AD11/GP[75]
IPD
DV
DD33
D3
C4
I/O/Z
HD15/MTXCLK/
AD12/GP[73]
IPD
DV
DD33
A4
A4
I/O/Z
HD9/MCOL/
PSTOP/GP[67]
IPD
DV
DD33
C6
C6
I/O/Z
HD11/MTXD3/
PCBE1/GP[69]
IPD
DV
DD33
C5
A5
I/O/Z
HD12/MTXD2/
PPAR/GP[70]
IPD
DV
DD33
D5
C5
I/O/Z
HD13/MTXD1/
AD14/GP[71]
IPD
DV
DD33
B4
B4
I/O/Z
HD14/MTXD0/
AD15/GP[72]
IPD
DV
DD33
D4
B5
I/O/Z
HR/W/MRXCLK/
AD8/GP[77]
IPD
DV
DD33
A3
A3
I/O/Z
HHWIL/MRXDV/
AD13/GP[74]
IPD
DV
DD33
C4
D3
I/O/Z
HCNTL0/MRXER/
AD10/GP[76]
IPD
DV
DD33
B3
B2
I/O/Z
HD10/MCRS/
PSERR/GP[68]
IPD
DV
DD33
B5
B6
I/O/Z
HINT/MRXD3/
AD6/GP[82]
IPU
DV
DD33
C2
D2
I/O/Z
HRDY/MRXD2/
PCBE0/GP[80]
IPU
DV
DD33
D2
C3
I/O/Z
HDS1/MRXD1/
AD7/GP[79]
IPU
DV
DD33
B2
B3
I/O/Z
HDS2/MRXD0/
AD9/GP[78]
IPU
DV
DD33
C3
C2
I/O/Z
HCS/MDCLK/
AD5/GP[81]
IPU
DV
DD33
C1
D1
I/O/Z
HAS/MDIO/
AD3/GP[83]
IPU
DV
DD33
D1
C1
I/O/Z
(1)
(2)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see
Section 3.9.1
,
Pullup/Pulldown Resistors
.
Specifies the operating I/O supply voltage for each signal
(3)
Device Overview
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