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TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 4, AEM[2:0] = 100)
SIGNAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 4, AEM[2:0] = 100)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., PCIEN, AEAW[2:0], AEM[2:0], etc.). For
more details, see
Section 3.7
,
Multiplexed Pin Configurations
.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
G1/EM_A[1]/
(ALE)/GP[9]/
(AEAW1/PLLMS1)
IPD
DV
DD33
A16
B20
I/O/Z
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
B1/EM_A[2]/
(CLE)/GP[8]/
(AEAW0/PLLMS0)
IPD
DV
DD33
B16
A20
I/O/Z
When used for EMIFA (NAND) , this pin is the Command Latch
Enable output (CLE).
EM_WAIT/
(RDY/BSY)
IPU
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
E15
D20
I/O/Z
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
EM_OE
D15
D19
I/O/Z
When used for EMIFA (NAND), this pin is read enable output (RE).
EM_WE
E14
C19
I/O/Z
When used for EMIFA (NAND), this pin is write enable output (WE).
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
NAND flash.
This is the chip select for the default boot and ROM boot modes.
G0/EM_CS2/
GP[12]
IPD
DV
DD33
C19
C22
I/O/Z
Note:
This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor
must
be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
NAND flash.
LCD_OE/EM_CS3/
GP[13]
IPD
DV
DD33
C18
D22
I/O/Z
Note:
This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor
must
be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
For EMIFA, it is Chip Select 4 output EM_CS4 for use with NAND
flash.
VSYNC/EM_CS4/
GP[32]
IPD
DV
DD33
E19
H22
I/O/Z
Note:
This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor
must
be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and
GPIO.
For EMIFA, it is Chip Select 5 output EM_CS5 for use with NAND
flash.
HSYNC/EM_CS5/
GP[33]
IPD
DV
DD33
F19
J22
I/O/Z
Note:
This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor
must
be used to ensure the
EM_CSx function defaults to an inactive (high) state.
(1)
(2)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see
Section 3.9.1
,
Pullup/Pulldown Resistors
.
Specifies the operating I/O supply voltage for each signal
(3)
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