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P
4.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
(1)
High-level output voltage (3.3V I/O)
DV
DD33
= MIN, I
OH
= MAX
High-level output voltage (1.8V I/O)
DV
DD18
= MIN, I
OH
= MAX
High-level output voltage (1.8V I/O
DV
DDR
= MIN, I
OH
= MAX
DDR2)
Low-level output voltage (3.3V I/O)
DV
DD33
= MIN, I
OL
= MAX
Low-level output voltage (1.8V I/O)
DV
DD18
= MIN, I
OL
= MAX
Low-level output voltage (1.8V I/O
DV
DDR
= MIN, I
OL
= MAX
DDR2)
V
= V
to DV
DD
without opposing
internal resistor
V
= V
to DV
(2)
with opposing internal
Input current
pullup resistor
V
= V
to DV
with opposing internal
pulldown resistor
(2)
VCLK, GPIO[48]/CLK_OUT0,
GPIO[8]/EM_CS5/VLYNQ_CLK,
EM_A[21:14]/VLYNQ_(TX/RX)D[3:0]
High-level output current
DDR2
All other peripherals
VCLK, GPIO[48]/CLK_OUT0,
GPIO[8]/EM_CS5/VLYNQ_CLK,
EM_A[21:14]/VLYNQ_(TX/RX)D[3:0]
Low-level output current
DDR2
All other peripherals
I/O Off-state output current
V
O
= DV
DD
or V
SS
Core (CV
, APLLREFV, V
,
V
DDA1P2LDD
, CV
DDDSP
) supply
CV
DD
= 1.2 V, DSP clock = 594 MHz
current
(4)
3.3V I/O (DV
D(4)
, USB_DV
DDA3P3
)
DV
DD
= 3.3 V, DSP clock = 594 MHz
supply current
1.8V I/O (DV
DD18
, DV
DDR2
,
DDR_V
DDDLL
,
DV
DD
= 1.8 V, DSP clock = 594 MHz
USB_V
, MXVDD, M24VDD)
supply current
(4)
Input capacitance
Output capacitance
TMS320DM6446
Digital Media System on-Chip
SPRS283–DECEMBER 2005
MIN
TYP
MAX
UNIT
V
V
DV
DD
- 0.2
DV
DD
- 0.45
DDR_VREF
+ 0.643
V
OH
V
0.2
0.45
V
V
V
OL
DDR_VREF
- 0.643
V
1
μA
I
I
TBD
μA
TBD
μA
8
mA
I
OH
-13.4
mA
mA
4
8
mA
I
OL
13.4
mA
mA
μA
4
I
OZ
±
20
I
CDD
TBD
mA
I
DDD
TBD
mA
I
DDD
TBD
mA
C
i
C
o
10
10
pF
pF
(1)
(2)
(3)
(4)
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
This pin is an internal LDO output and connected via 1 μF capacitor to USB_V
.
Measured with average activity (50% high/50% low power) at 25
°
C case temperature and TBD-MHz EMIFA for -594 speed. This model
represents a device performing high-MPU/DSP-activity operations 50% of the time, and the remainder performing low-MPU/DSP-activity
operations. The high/low-MPU/DSP-activity models are defined as follows:
High-MPU/DSP-Activity Model:
–
MPU: TBD
–
DSP: TBD
Low-MPU/DSP-Activity Model:
–
MPU: TBD
–
DSP: TBD
The actual current draw is highly application-dependent. For more details on core and I/O activity, see the
DM644xPower Consumption
Summary
application report (literature number SPRATBD).
84
Device Operating Conditions