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2.3 Memory Map Summary
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 2-2
shows the memory map address ranges of the TCI6482 device. The external memory
configuration register address ranges in the TCI6482 device begin at the hex address location 0x7000
0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller.
Table 2-2. TCI6482 Memory Map Summary
MEMORY BLOCK DESCRIPTION
BLOCK SIZE (BYTES)
1024K
32K
7M - 32K
2M
4M
32K
1M - 32K
32K
1M - 32K
8M
4M
12.5M
256K
256K
256K
256K
128K
512
256K - 512
512
64K
32K
96K
32K
32K
32K
32K
256K
256K
256K
16K
256K
512
256K - 512
128K
128K
256K
256K
256K
4K
2K
2K
HEX ADDRESS RANGE
0000 0000 - 000F FFFF
0010 0000 - 0010 7FFF
0010 8000 - 007F FFFF
0080 0000 - 009F FFFF
00A0 0000 - 00DF FFFF
00E0 0000 - 00E0 7FFF
00E0 8000 - 00EF FFFF
00F0 0000 - 00F0 7FFF
00F0 8000 - 00FF FFFF
0100 0000 - 017F FFFF
0180 0000 - 01BF FFFF
01C0 0000 - 0287 FFFF
0288 0000 - 028B FFFF
028C 0000 - 028F FFFF
0290 0000 - 0293 FFFF
0294 0000 - 0297 FFFF
0298 0000 - 0299 FFFF
029A 0000 - 029A 01FF
029A 0200 - 029B FFFF
029C 0000 - 029C 01FF
029C 0200 - 029C FFFF
02A0 0000 - 02A0 7FFF
02A0 8000 - 02A1 FFFF
02A2 0000 - 02A2 7FFF
02A2 8000 - 02A2 FFFF
02A3 0000 - 02A3 7FFF
02A3 8000 - 02A3 FFFF
02A4 0000 - 02A7 FFFF
02A8 0000 - 02AB FFFF
02AC 0000 - 02AF FFFF
02B0 0000 - 02B0 3FFF
02B0 4000 - 02B3 FFFF
02B4 0000 - 02B4 01FF
02B4 0200 - 02B7 FFFF
02B8 0000 - 02B9 FFFF
02BA 0000 - 02BB FFFF
02BC 0000 - 02BF FFFF
02C0 0000 - 02C3 FFFF
02C4 0000 - 02C7 FFFF
02C8 0000 - 02C8 0FFF
02C8 1000 - 02C8 17FF
02C8 1800 - 02C8 1FFF
Reserved
Internal ROM
Reserved
Internal RAM (L2) [L2 SRAM]
Reserved
L1P SRAM
Reserved
L1D SRAM
Reserved
Reserved
C64x+ Megamodule Registers
Reserved
HPI Control Registers
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
PLL1 Controller (including Reset Controller) Registers
Reserved
PLL2 Controller Registers
Reserved
EDMA3 Channel Controller Registers
Reserved
EDMA3 Transfer Controller 0 Registers
EDMA3 Transfer Controller 1 Registers
EDMA3 Transfer Controller 2 Registers
EDMA3 Transfer Controller 3 Registers
Reserved
Chip-Level Registers
Device State Control Registers
GPIO Registers
I2C Data and Control Registers
UTOPIA Control Registers
Reserved
VCP2 Control Registers
TCP2 Control Registers
Reserved
PCI Control Registers
Reserved
EMAC Control
EMAC Control Module Registers
MDIO Control Registers
Device Overview
10
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