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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-4. EDMA3 Channel Controller Registers (continued)
HEX ADDRESS RANGE
02A0 081C
02A0 0820
02A0 0824
02A0 0828
02A0 082C - 02A0 0FFC
02A0 1000
02A0 1004
02A0 1008
02A0 100C
02A0 1010
02A0 1014
02A0 1018
02A0 101C
02A0 1020
02A0 1024
02A0 1028
02A0 102C
02A0 1030
02A0 1034
02A0 1038
02A0 103C
02A0 1040
02A0 1044
02A0 1048 - 02A0 104C
02A0 1050
02A0 1054
02A0 1058
02A0 105C
02A0 1060
02A0 1064
02A0 1068
02A0 106C
02A0 1070
02A0 1074
02A0 1078
02A0 107C
02A0 1080
02A0 1084
02A0 1088
02A0 108C
02A0 1090
02A0 1094
02A0 1098 - 02A0 1FFF
02A0 2000 - 02A0 2097
02A0 2098 - 02A0 21FF
02A0 2200 - 02A0 2297
02A0 2298 - 02A0 23FF
ACRONYM
MPPA4
MPPA5
MPPA6
MPPA7
-
ER
ERH
ECR
ECRH
ESR
ESRH
CER
CERH
EER
EERH
EECR
EECRH
EESR
EESRH
SER
SERH
SECR
SECRH
-
IER
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
IEVAL
-
QER
QEER
QEECR
QEESR
QSER
QSECR
-
-
-
-
-
REGISTER NAME
Memory Protection Page Attribute Register 4
Memory Protection Page Attribute Register 5
Memory Protection Page Attribute Register 6
Memory Protection Page Attribute Register 7
Reserved
Event Register
Event Register High
Event Clear Register
Event Clear Register High
Event Set Register
Event Set Register High
Chained Event Register
Chained Event Register High
Event Enable Register
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
Interrupt Enable Register
Interrupt Enable High Register
Interrupt Enable Clear Register
Interrupt Enable Clear High Register
Interrupt Enable Set Register
Interrupt Enable Set High Register
Interrupt Pending Register
Interrupt Pending High Register
Interrupt Clear Register
Interrupt Clear High Register
Interrupt Evaluate Register
Reserved
QDMA Event Register
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
Shadow Region 0 Channel Registers
Reserved
Shadow Region 1 Channel Registers
Reserved
C64x+ Peripheral Information and Electrical Specifications
114
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