www.ti.com
8.9.2
DDR2 Memory Controller Peripheral Register Description(s)
8.9.3
DDR2 Memory Controller Electrical Data/Timing
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
The master peripherals that need to implement this workaround are HPI, PCI, and VLYNQ.
Table 8-40. DDR2 Memory Controller Registers
HEX ADDRESS RANGE
7800 0000
7800 0004
7800 0008
7800 000C
7800 0010
7800 0014
7800 0018
7800 0020
7800 0024 - 7800 004C
7800 0050 - 7800 0078
7800 007C - 7800 00BC
7800 00C0 - 7800 00E0
7800 00E4
7800 00E8 - 7800 00FC
7800 0100 - 7FFF FFFF
ACRONYM
MIDR
DMCSTAT
SDCFG
SDRFC
SDTIM1
SDTIM2
-
BPRIO
-
-
-
-
DMCCTL
-
-
REGISTER NAME
DDR2 Memory Controller Module and Revision Register
DDR2 Memory Controller Status Register
DDR2 Memory Controller SDRAM Configuration Register
DDR2 Memory Controller SDRAM Refresh Control Register
DDR2 Memory Controller SDRAM Timing 1 Register
DDR2 Memory Controller SDRAM Timing 2 Register
Reserved
DDR2 Memory Controller Burst Priority Register
Reserved
Reserved
Reserved
Reserved
DDR2 Memory Controller Control Register
Reserved
Reserved
The
Implementing DDR2 PCB Layout on the TMS320TCI6482
application report (literature number
SPRAAA9
) specifies a complete DDR2 interface solution for the TCI6482 as well as a list of compatible
DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2 interface
timings in this solution are met; therefore, no electrical data/timing information is supplied here for this
interface.
TI
only
supports designs that follow the board design guidelines outlined in the SPRAAA9
application report.
C64x+ Peripheral Information and Electrical Specifications
158
Submit Documentation Feedback