- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98293 > TS83102G0BCGL (E2V TECHNOLOGIES PLC) 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 PDF資料下載
參數(shù)資料
| 型號(hào)： | TS83102G0BCGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152 |
| 文件頁數(shù)： | 32/60頁 |
| 文件大小： | 1510K |
| 代理商： | TS83102G0BCGL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
38
0830E–BDC–06/07
TS83102G0B
e2v semiconductors SAS 2007
The DRRB’s rising edge occurs when the external encoding clock input (CLK/CLKB) is LOW : the
Data Ready output’s first rising edge occurs after half a clock period on the clock’s falling edge, and a
TDR delay time of 410 ps, as defined above.
The DRRB’s rising edge occurs when the external encoding clock input (CLK/CLKB) is HIGH : the
Data Ready output’s first rising edge occurs after one clock period on the clock’s falling edge, and a
TDR delay time of 410 ps.
Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data corre-
sponding to the first acquisition (N), after a Data Ready signal restart (rising edge), is always strobed by
the third rising edge of the Data Ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output data (zero
crossing point) to the rising or falling edge of the differential Data Ready signal (DR/DRB) [zero crossing
point].
Note:
For normal initialization of the Data Ready output signal, the external encoding clock signal frequency and
level must be controlled. The minimum encoding clock sampling rate for the ADC is 150 Msps, due to the
internal Sample and Hold drop rate. Consequently the clock cannot be stopped.
13.2.3
Timing Diagram
Figure 13-1. TS83102G0B Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at LOW Level
Figure 13-2. TS83102G0B Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at HIGH Level
N - 4
N - 3
N - 2
N - 1
N
N + 1
VIN/VINB
CLK/CLKB
Digital
Outputs
Data Ready
DR/DRB
Data Ready
Reset
TA = 160 ps
N
N + 1
N + 2
N + 3
N - 5
TOD = 360 ps
TDR = 410 ps
TRDR = 1000 ps
1 ns
TC = 500 ps
TC1 TC2
TPD = 4.0 Clock Period
TOD = 360 ps
500 ps
TDR = 410 ps
TD1 = TC1 + TDR - TOD
= TC1 + 50 ps = 300 ps
TD2 = TC2 + TOD - TDR
= TC2 - 50 ps = 200 ps
N - 4
N - 3
N - 2
N - 1
N
N + 1
N - 5
500 ps
TD2 = TC2 + TOD - TDR
= TC2 - 50 ps = 200 ps
TD1 = TC1 + TDR - TOD
= TC1 + 50 ps = 300 ps
TDR = 410 ps
TPD = 4.0 Clock Periods
TOD = 360 ps
TRDR = 1000 ps
1 ns
TDR = 410 ps
TOD = 360 ps
TA = 160 ps
N
N + 1
N + 2
N + 3
TC = 500 ps
TC1
TC2
VIN/VINB
CLK/CLKB
Digital
Outputs
Data Ready
DR/DRB
Data Ready
Reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS83110CZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
| TS83110MZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
| TS83110VZT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28 |
| TS83110MZB/T | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDSO28 |
| TS83110VS | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。