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參數(shù)資料
| 型號： | TS83102G0BCGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152 |
| 文件頁數(shù)： | 35/60頁 |
| 文件大小： | 1510K |
| 代理商： | TS83102G0BCGL |
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40
0830E–BDC–06/07
TS83102G0B
e2v semiconductors SAS 2007
13.3.2
Dynamic Issues:
Input Impedance and VSWR
The TS83102G0B analog input features a 100
(±2%) differential input impedance
(2 x 50
// 0.3 pF). Each analog input (VIN,VINB) is terminated by 50 single-ended (100 differen-
tial) resistors (±2% matching) soldered into the package cavity.
The transmission lines of the ADC package’s analog inputs feature a 50
controlled impedance. Each
single-ended die input pad capacitance (taking into account the ESD protection) is
0.3 pF. This leads to a global input VSWR (including ball, package and bounding) of less than 1.2 from
DC up to 2.5 GHz.
13.4
Clock Inputs (CLK/CLKB)
The TS83102G0B clock inputs are designed for either single-ended or differential operation. The
device’s clock inputs are on-chip 100
(2 x 50 ) differentially terminated. The termination mid point is
AC coupled to ground through a 40 pF on-chip capacitor. Therefore, either ground or different common
modes can be used (ECL, LVDS).
Note:
As long as V
IH remains below the 1V peak, the ADC clock can be DC coupled. If VIH is higher than the 1V
peak, it is necessary to AC couple the signal via 100 pF capacitors, for example, and to bias CLK and
CLKB:
- CLK biased to ground via a 10 k
resistor
- CLKB biased to ground via a 10 k
resistor and to V
EE via a 100 k resistor.
However, logic ECL or LVDS square wave clock generators are not recommended because of poor jitter
performances. Furthermore, the propagation times of the biasing tees used to offset the common mode
voltage to ECL or LVDS levels may not match. A very low-phase noise (low jitter) sinewave input signal
should be used for enhanced SNR performance, when digitizing high frequency analog inputs. Typically,
when using a sinewave oscillator featuring a
-135 dBc/Hz phase noise, at 20 KHz from the carrier, a global jitter value (including the ADC and the
generator) of less than 200 fs RMS has been measured. If the clock signal frequency is at fixed rates, it
is recommended to narrow-band filter the signal to improve jitter performance.
Note:
The clock input buffer’s 100
termination load is on-chip and mid-point AC coupled (40 pF) to the chip’s
ground plane, whereas the analog input buffer’s 100
termination is soldered inside the package cavity
and mid-point DC coupled to the package ground plane.Therefore, driving the analog input in single-ended
mode does not perturb the chip’s ground plane (since the termination mid-point is connected to the pack-
age ground plane). However, driving the clock input in single-ended mode does perturb the chip’s ground
plane (since the termination mid-point is AC coupled to the chip’s ground plane). Therefore, it is required to
drive the clock input in differential mode for minimum chip ground plane perturbation (a 4 dBm maximum
operation is recommended). The typical clock input power is 0 dBm. The minimum operating clock input
power is -4 dBm (equivalent to a 250 mV minimum swing amplitude), to avoid SNR performance degrada-
tions linked to the clock signal’s slew rate.
A single to differential balun with sqrt (2) ratio may be used (featuring a 50
input impedance with 100
differential termination).
For instance:
4 dBm is equivalent to 1 Vpp into 50
and 1.4 Vpp into 100 termination (secondary).
0 dBm is equivalent to 0.632 Vpp into 50
and 0.632 x sqrt (2) = 0.894 Vpp into 100 termination
(secondary), ± 0.226V at each clock input.
The recommended clock input’s common mode is ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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