參數(shù)資料
型號: TS83102G0BCGL
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152
文件頁數(shù): 45/60頁
文件大?。?/td> 1510K
代理商: TS83102G0BCGL
5
0830E–BDC–06/07
e2v semiconductors SAS 2007
TS83102G0B
7.3
Electrical Operating Characteristics
V
CC = 5V ; VPLUSD = 0V (unless otherwise specified). ADC performances are independent of VPLUSD common mode
voltage and performances are guaranteed within the limits of the specified V
PLUSD range (from -0.9V to 1.7V);
V
EE = DVEE = -5V; VIN - VINB = 500 mVpp (full-scale single-ended or differential input);
clock inputs differential driven; analog-input single-ended driven.
Parameter
Test
Level
Symbol
Min
Typ
Max
Unit
Resolution
10
Bits
Power Requirements
Positive supply voltage
- analog
- digital (ECL)
- digital (LVDS)
1
4
V
CC
VPLUSD
4.75
5
- 0.8
1.45
5.25
V
Positive supply current
- analog
- digital
1
IVCC
I
VPLUSD
138
154
205
200
mA
Negative supply voltage
- analog
- digital
1
V
EE
DVEE
-5.25
-5
-4.75
V
Negative supply current
- analog
- digital
1
VEE
IDVEE
615
160
750
200
mA
Power dissipation
- ECL
- LVDS
1
4
P
D
4.6
5.0
5.2
5.7
W
Analog Inputs
Full-scale input voltage range (differential mode)
(0 V common mode voltage)
4
V
IN,
VINB
- 125
125
mV
Full-scale input voltage range (single-ended input
option)
(0 V common mode voltage)
4
V
IN,
V
INB
- 250
0
250
mV
Analog input power level (50
single-ended)
4
PIN
- 2
dBm
Analog input capacitance (die)
4
C
IN
0.3
pF
Input leakage current
4
I
IN
10
A
Input resistance
- single-ended
- differential
4
R
IN
R
IN
49
98
50
100
51
102
Clock Inputs
Logic common mode compatibility for clock inputs
Differential ECL to LVDS
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