參數(shù)資料
型號： TVP3030-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器）
文件頁數(shù)： 22/107頁
文件大?。?/td> 689K
代理商： TVP3030-175
2–6
The clock generators use a modified M over (N
×
2
P
) scheme to enable a wide range of precise frequencies.
(Appendix A provides a listing of all frequencies that can be synthesized and the register values for each.)
The advanced PLLs utilize an internal loop filter to provide maximum noise immunity and minimum jitter.
Except for the reference crystal or oscillator, no external components or adjustments are necessary. Each
PLL can be independently enabled or disabled for maximum system flexibility. Figure 2–1 illustrates the
TVP3030 clocking scheme. The PLLs are programmed through a group of four registers in the TVP3030
indirect register map. The registers are listed in the following table.
Table 2–6. PLL Top Level Registers
INDEX
REGISTER
0x2C
PLL address register (PAR)
0x2D
Pixel clock PLL data register (PPD)
0x2E
MCLK PLL data register (MPD)
0x2F
Loop clock PLL data register (LPD)
The PLL address register (PAR) is used to point to the M, N, P, and status registers of each PLL. This register
allows read and write access and contains three 2-bit pointers, one for each PLL, according to the Table 2–7.
Each pointer may be programmed independently.
Table 2–7. PLL Address Register
(Index: 0x2C, Access: R/W, Default: Uninitialized)
PAR BITS
POINTER
1–0
Pixel clock PLL data register pointer
3–2
MCLK PLL data register pointer
5–4
Loop clock PLL data register pointer
Each PLL data register pointer points its associated PLL to one of its four PLL registers according to
Table 2–8.
Table 2–8. PLL Data Register Pointer Format
BIT 1
BIT 0
REGISTER
0
0
N value register
0
1
M value register
1
0
P value register
1
1
Status register (read-only)
Once the PLL data register pointers are set, the selected registers are accessed through the pixel clock PLL
data register (index: 0x2D), MCLK PLL data register (index: 0x2E) or the loop clock PLL data register (index:
0x2F). The PLL data register pointer bits are independently auto-incremented following a write cycle to the
corresponding PLL data register. The current state of each pointer can be identified by reading the PLL
address register (index: 0x2C). The PLL data register pointer bits do not auto increment following a read
cycle of the PLL data registers.
The most efficient way to program the pixel clock PLL is to first write zeros to PLL address register bits
PAR(1,0) followed by three consecutive writes to the pixel clock PLL data register to program the N, M, and
P-value registers. Following the third write, the pixel clock PLL pointer will point to the read-only status
register. The status register can then be polled until the LOCK bit is set (the pointer does not auto-increment
on reads). For test purposes, the pixel clock PLL can be output on the PCLKOUT terminal by programming
the pixel clock PLL P value register bit 6 to a logic 1.
相關(guān)PDF資料
PDF描述
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3030-175PPA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3030-175PPM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC
TVP3030-230PPA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3030-250MEP 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3033 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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