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參數(shù)資料
| 型號： | TVP3030-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 28/107頁 |
| 文件大小： | 689K |
| 代理商： | TVP3030-175 |
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2–12
The dot clock frequency can either be generated by the on-chip pixel clock PLL or by an external clock
source. The following two parameters can be easily calculated from the above parameters.
LCLK frequency (MHz) (F
L
) – frequency at which pixel bus is loaded by TVP3030
RCLK frequency (MHz) (F
R
) – frequency at RCLK output terminal of TVP3030
The LCLK frequency is given by
B
W
FL
FD
The RCLK frequency is F
L
times the external divide factor. If no external divide factor, K = 1.
B
W
FR
K
FL
K
FD
The N and M values are set as follows:
N
65
4
W
B
M
61
The P and Q frequency dividers must be programmed so that the VCO is within its operating range. The
VCO frequency is post-scaled by the P-divider followed by the Q-divider. The P-divider register (P) can take
on values of 0, 1, 2, or 3 which correspond to division factors of 1, 2, 4, or 8. The Q-divider register (Q) is
stored in bits 2 – 0 of the MCLK/loop clock control register (index: 0x39) and can take on values of 0, 1, 2,
. . ., 7 which correspond to division factors of 2, 4, 6, . . ., 16. The total post scalar frequency division factor
is:
F
VCO
4
F
D
Z
2
P
1
(Q
1)
(65
N)
K
Next, set F
VCO
to the lower limit of 110 MHz and solve for Z:
27.5
(65
F
D
Z
N)
K
Finally, determine the P and Q values:
IF Z
16 then P
largest integer less than log
2
(Z), Q
smallest integer greater thanZ
0
IF Z
16 then P
3, Q
16
16
Set bits 7,6 of the N-value register to 1,1 (default). Set LES1 and LES0 in the M-value register (bits 7,6) to
0,0 (default). Set bits 7–2 of the P-value register to 1111 00. This enables the PLL to oscillate and disables
the LCLK edge synchronizer function, which is only used for packed-24 modes. To reset the PLL, set bit 7
of the P-value register to logic 0.
2.5.3.2
For packed-24 modes, the loop clock PLL is programmed according to Table 2–14. The LCLK edge
synchronizer delay (M-value register bits 7,6) depends on whether the graphics accelerator is driving the
VRAM shift clock (true color control register bit TCR5 is logic 0) or the TVP3030 is driving the VRAM shift
clock (TCR5 = logic 1). See Section 2.8.6 for a typical setup procedure for packed-24 modes.
Programming for Packed-24 Modes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3030-175PPA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3030-175PPM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| TVP3030-230PPA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3030-250MEP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3033 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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