參數(shù)資料
型號(hào)： TVP3030-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器）
文件頁(yè)數(shù)： 39/107頁(yè)
文件大?。?/td> 689K
代理商： TVP3030-175
2–23
2.8.7
The pixel port multiplexer is controlled by two 8-bit registers in the indirect register map (see Table 2–2). The
various multiplexing modes can be selected according to Table 2–16.
Multiplex-Control Registers
NOTE:
Multiplex-control register bit MCR6 determines which set of video controls are used
and how VGA7–VGA0 is latched. If MCR6 is logic 1, SYSBL, SYSVS, SYSHS are
used and these video controls and VGA7–VGA0 are latched by LCLK. This is
referred to as VGA mode 1. This mode of operation allows use of the loop clock PLL
in VGA mode. Bit MCR6 should be logic 1 for all modes utilizing the pixel bus
P127–P0.
If MCR6 is logic 0, VGABL, VGAVS, VGAHS are used and these video controls and
VGA7–VGA0 are latched by CLK0. This is referred to as VGA mode 2. VGA
mode 2 supports most graphics accelerators with integrated VGA and also
supports add-on graphics boards that receive the VGA pseudo-color data from a
separate VGA controller via a feature connector. VGA mode 2 is active at power-up
and after reset and is fully functional without any software intervention. VGA data
and video controls are received with a synchronous VGA clock.
For all modes, true-color control register bit TCR5 selects one of two timing modes
for the blank pipelining and pixel bus timing. See Figures 2–5 and 2–6
.
If TCR5 is logic 0 (default) it is assumed that the VRAM shift clock is sourced by
the graphics accelerator, and that SCLK from the TVP3030 is not being used. In
this case, the first sample of BLANK inactive and the first pixel group latched into
P127–P0 are assumed to coincide on the same rising edge of LCLK.
If TCR5 is logic 1, it is assumed that SCLK is used as the VRAM shift clock. In this
case, the TVP3030 must first sample BLANK in order to start toggling SCLK and
then latch the first pixel group into P127–P0. Therefore, the TVP3030 assumes
there will be a 2-LCLK delay between the first sample of BLANK inactive and the
latching of the first pixel group by LCLK. In this case, the TVP3030 inserts additional
pipeline delays to align the internal BLANK signal with the pixel data at the DACs.
The default condition after reset is for the palette bypass bit (MSC5) to select the
palette RAM for display. The default condition for the color-key function is to be
disabled and selecting palette bypass (CKC4 = CKC3 = CKC2 = CKC1 = CKC0 =
logic 0). The overall effect is to default to selecting the palette RAM since the two
are combined by a logical OR function. If direct-color mode is desired, then bit
MSC5 should be set to logic 1.
相關(guān)PDF資料
PDF描述
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3030-175PPA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3030-175PPM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC
TVP3030-230PPA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3030-250MEP 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3033 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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