參數(shù)資料
型號(hào): TVP3030-175
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE Exract(1600×1200,24位真彩色視頻接口調(diào)色器)
中文描述: 視頻接口調(diào)色板Exract(1600 × 1200,24位真彩色視頻接口調(diào)色器)
文件頁(yè)數(shù): 58/107頁(yè)
文件大?。?/td> 689K
代理商: TVP3030-175
2–42
2.13.3
An ID register with a hardwired code is provided that can be used as a software identification of the device
for different versions of the system design. The ID register is read only through index 0x3F. The value defined
for the TVP3030 is 0x30.
Identification Code
2.13.4
The silicon revision register (index: 0x01) is a read-only register that enables software to identify the silicon
revision of the TVP3030. The number in the register is initially 0x00. A major revision number is stored in
bits 7–4 and a minor revision number is stored in bits 3–0.
Silicon Revision
2.14 Reset
There are two ways to reset the TVP3030. The RESET input terminal can be used to perform a hardware
reset. Alternatively, the device has an integrated software reset function.
A hardware reset is initiated by pulling the RESET input terminal low. When RESET is pulled low all
TVP3030 registers go to default states. This reset is asynchronous, and any glitch on this terminal could
change the intended register setup. The default state at reset is VGA mode, and all default register settings
are given in Table 2–2. If a reset is desired at power up, an external resistor, capacitor, and diode network
can be connected to the RESET terminal. If TTL logic is employed to provide the signal to the RESET
terminal, a pull up resistor should be used to make sure that CMOS levels are achieved.
For a software reset, anytime the reset register (index: 0xFF) is written to, all registers are initialized to
TVP3030 default settings. The data written into the reset register is ignored.
2.15 Analog Output Specifications
The DAC outputs are controlled by three current sources (only two for IOR and IOB) as shown in
Figure 2–12. The default condition is to have 0 IRE difference between blank and black levels, which is
shown in Figure 2–13. If a 7.5-IRE pedestal is desired, it can be selected by setting bit 4 of the
general-control register. This video output is shown in Figure 2–14.
A resistor (R
SET
) is needed between the FS ADJUST terminal and GND to control the magnitude of the
full-scale video signal. The IRE relationships in Figures 2–13 and 2–14 are maintained regardless of the
full-scale output current.
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