參數(shù)資料
型號(hào)： TVP3030-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器）
文件頁(yè)數(shù)： 30/107頁(yè)
文件大?。?/td> 689K
代理商： TVP3030-175
2–14
For high resolution modes, in both configurations, the pixel data is received from VRAM and the loop clock
PLL is used to adjust RCLK so that the received LCLK is aligned with the internal dot clock. The loop clock
PLL must be selected for output on the RCLK terminal. The pixel clock PLL (or an external clock source)
should be selected as the dot clock source.
Graphics
Accelerator
VRAM
VGA(7–0)
LCLK
CLK0
P(127–0)
MCLK
RCLK
TVP3030
Figure 2–3. Typical Configuration – VRAM Clocked by Accelerator
Graphics
Accelerator
VRAM
VGA(7–0)
LCLK
CLK0
P(127–0)
MCLK
RCLK
TVP3030
SCLK
Figure 2–4. Typical Configuration – VRAM Clocked by TVP3030
2.6
The TVP3030 provides two output clock signals and one input clock signal for controlling the frame-buffer
interface: SCLK, RCLK, and LCLK. Clocking of the frame buffer interface is discussed in Section 2.6.1. The
128-bit pixel bus allows many operational display modes as defined in Section 2.8 and Table 2–16. The pixel
latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes in which multiple pixels
are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the pixels that reside
on the low numbered pixel port terminals. For example, in an 8-bit-per-pixel pseudo-color mode with an 8:1
multiplex ratio, the pixel display sequence is P(7–0), P(15–8), P(23–16), P(31–24), P(39–32), P(47–40),
P(55–48), and P(63–56).
Frame-Buffer Interface
The TVP3030 frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This
can be controlled by general-control register (GCR) bit 3. See Section 2.8.1 for details of operation.
2.6.1
The TVP3030 provides SCLK and RCLK, allowing for flexibility in the frame buffer interface timing. For the
pixel port (P127–P0), data is always latched on the rising edge of LCLK. If bit TCR5 in the true-color control
register is logic 1, use of SCLK is assumed and internal pipeline delay is added to sync and blank to account
for the delay in the generation of SCLK. If TCR5 is logic 0 (default), then this pipeline delay is not added,
and SCLK should not be used.
Frame-Buffer Clocking
相關(guān)PDF資料
PDF描述
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3030-175PPA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3030-175PPM 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Converter IC
TVP3030-230PPA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3030-250MEP 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3033 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Video Interface Palette
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