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參數(shù)資料
| 型號： | UPD753036GC |
| 廠商： | NEC Corp. |
| 英文描述： | DIODE ZENER SINGLE 500mW 47Vz 2.7mA-Izt 0.05 0.1uA-Ir 36Vr DO35-GLASS 5K/REEL |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 22/88頁 |
| 文件大?。?/td> | 483K |
| 代理商： | UPD753036GC |
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22
μ
PD753036, 753036(A)
Data Sheet U11353EJ4V0DS00
6.2 Clock Generator
The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is
shown in Figure 6-1.
The operation of the clock generation circuit is determined by the processor clock control register (PCC) and
system clock control register (SCC).
Two types of system clocks are available: main system clock and subsystem clock.
Furthermore, the instruction execution time can be changed.
0.95, 1.91, 3.81, 15.3
μ
s (main system clock: at 4.19 MHz operation)
0.67, 1.33, 2.67, 10.7
μ
s (main system clock: at 6.0 MHz operation)
122
μ
s (subsystem clock: at 32.768 kHz operation)
Figure 6-1. Clock Generator Block Diagram
Note
Instruction execution
V
DD
V
DD
XT1
X1
XT2
X2
f
XT
f
X
Subsystems
clock oscillator
Main system
clock oscillator
4
HALT
Note
STOP
Note
WM.3
SCC
SCC3
SCC0
PCC0
PCC1
PCC2
PCC3
PCC2,
PCC3
Clear
STOP F/F
Q
S
R
Oscillation
stop
HALT F/F
S
R
Wait release signal from BT
RESET signal
Standby release signal from
interrupt control circuit
· CPU
· INT0 noise eliminator
· Clock output circuit
Φ
1/4
Divider
1/1~1/4096
Divider
1/21/41/16
· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· LCD controller/driver
· A/D converter
· INT0 noise eliminator
· Clock output circuit
LCD controller/driver
Watch timer
PCC
Q
Selector
Selector
I
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