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參數(shù)資料
| 型號(hào)： | UPD753036GC |
| 廠商： | NEC Corp. |
| 英文描述： | DIODE ZENER SINGLE 500mW 47Vz 2.7mA-Izt 0.05 0.1uA-Ir 36Vr DO35-GLASS 5K/REEL |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 41/88頁(yè) |
| 文件大小： | 483K |
| 代理商： | UPD753036GC |
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41
μ
PD753036, 753036(A)
Data Sheet U11353EJ4V0DS00
Table 9-1. Status of Each Device After Reset (1/2)
Hardware
RESET Signal Generation
in the Standby Mode
RESET Signal Generation
in Operation
Program counter (PC)
Sets the low-order 6 bits of
program memory’s address
0000H to the PC13-PC8 and the
contents of address 0001H to
the PC7-PC0.
Sets the low-order 6 bits of
program memory’s address
0000H to the PC13-PC8 and the
contents of address 0001H to
the PC7-PC0.
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0-SK2)
0
0
Interrupt status flag (IST0, 1)
0
0
Bank enable flag (MBE, RBE)
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
1000B
1000B
Data memory (RAM)
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
0, 0
Basic interval
Counter (BT)
Undefined
Undefined
timer/watch-
Mode register (BTM)
0
0
dog timer
Watchdog timer enable flag (WDTM)
0
0
Timer/event
Counter (T0)
0
0
counter (T0)
Modulo register (TMOD0)
FFH
FFH
Mode register (TM0)
0
0
TOE0, TOUT F/F
0, 0
0, 0
Timer/event
Counter (T1)
0
0
counter (T1)
Modulo register (TMOD1)
FFH
FFH
Mode register (TM1)
0
0
TOE1, TOUT F/F
0, 0
0, 0
Timer/event
Counter (T2)
0
0
counter (T2)
Modulo register (TMOD2)
FFH
FFH
High level period setting modulo
register (TMOD2H)
FFH
FFH
Mode register (TM2)
0
0
TOE2, TOUT F/F
0, 0
0, 0
REMC, NRZ, NRZB
0, 0, 0
0, 0, 0
TGCE
0
0
Watch timer
Mode register (WM)
0
0
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