
138
μ
PD75518(A)
6. STANDBY FUNCTION
To reduce the power consumption when the program is in the wait state, the
μ
PD75518(A) has two standby
modes, STOP and HALT.
6.1 SETTING OF STANDBY MODES AND OPERATION STATUSES
Table 6-1 Operation Statuses in the Standby Mode
Instruction for setting
System clock at setting
HALT instruction
This mode can be set when either the main
system clock or the subsystem clock is
used.
Only CPU clock
Φ
is stopped (with oscilla-
tion continued).
Operation is continued (to set IRQBT at
reference time intervals).
Operation is possible only when the main
system clock operates or external SCK0 is
used.
Operation is possible only when the main
system clock operates.
Operation is possible only when the main
system clock operates.
Operation is possible.
Operation is possible only when the main
system clock operates.
Operation is possible only when the main
system clock operates.
STOP mode
HALT mode
STOP instruction
This mode can be set only when the main
system clock is used.
Only the main system clock is stopped.
Operation is stopped.
Operation is possible only when external
SCK0 input is selected for the serial clock.
Operation is possible only when external
SCK1 input is selected for the serial clock.
Operation is possible only when TI0 pin
input is selected for the count clock.
Operation is possible only when f
XT
is se-
lected for the count clock.
Operation is stopped.
Operation is stopped.
Clock generator
Basic interval
timer
Serial interface
(Channel 0)
Serial interface
(Channel 1)
Timer/event
counter
Watch timer
A/D converter
Timer/pulse
generator
External interrupt
CPU
INT0 is disabled. INT1, INT2, and INT4 are enabled.
Operation is stopped.
Interrupt request signals transmitted from hardware, which are enabled by interrupt
enable flags, or RESET input.
Opera-
tion
status
Release signal