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87
μ
PD75518(A)
Fig. 4-35 Format of Serial Operation Mode Register 0 (CSIM0) (2/3)
Serial clock selection bit (W)
Note
The values in parentheses are for f
X
= 4.19 MHz or 6.0 MHz.
Serial interface operation mode selection bit (W)
Remark
×
: Don’t care
Wake-up function specification bit (W)
Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode, the
BUSY signal is output until the next falling edge of the serial clock (SCK0) appears after release
of BUSY is directed. Before setting WUP = 1, be sure to confirm that the SB0 (or SB1) pin is high
after releasing BUSY.
Serial clock
SBI mode
2-wire serial I/O mode
3-wire serial I/O mode
External clock applied to SCK0 pin
Timer/event counter output (T0)
f
X
/2
4
(262 kHz or 375 kHz)
Note
f
X
/2
3
(524 kHz or 750 kHz)
Note
CSIM01
CSIM00
f
X
/2
6
(65.5 kHz or
93.8 kHz)
Note
SCK0 pin mode
0
0
1
1
0
1
0
1
Input
Output
Operation mode
CSIM04
CSIM03
CSIM02
Shift register bit
sequence
SIO0
7-0
XA
(Transfer starting
with MSB)
SIO0
0-7
XA
(Transfer starting
with LSB)
SIO0
7-0
XA
(Transfer starting
with MSB)
SIO0
7-0
XA
(Transfer starting
with MSB)
SI0 pin function
0
1
1
0
1
0
1
×
0
1
0
1
SO0 pin function
SO0/P02
(CMOS output)
SB0/P02
(N-ch open-drain
input/output)
P02 input
SB0/P02
(N-ch open-drain
input/output)
P02 input
SI0/P03
(Input)
P03 input
SB1/P03
(N-ch open-drain
input/output)
P03 input
SB1/P03
(N-ch open-drain
input/output)
3-wire serial I/O
mode
SBI mode
2-wire serial I/O
mode
Sets IRQCSI0 each time serial transfer is completed in each mode.
Used in the SBI mode only to set IRQCSI0 only when an address received after bus release matches
the data in the slave address register (wake-up state). SB0/SB1 goes to high-impedance state.
WUP
0
1