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28
μ
PD75518(A)
Fig. 3-2 Program Memory Map
Caution The start address of an interrupt vector shown above consists of 14 bits. So, the start address
must be set within a 16K-byte space (0000H to 3FFFH).
Remark
In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address
with only the low-order 8 bits of the PC changed.
MBE
RBE
7
6
0000H
MBE
RBE
0002H
MBE
RBE
0004H
MBE
RBE
0006H
MBE
RBE
0008H
MBE
RBE
000AH
007FH
0080H
0020H
0FFFH
1000H
2FFFH
3000H
5FFFH
6000H
0
Internal reset start address (high-order 6 bits)
Internal reset start address (low-order 8 bits)
INTBT/INT4 start address (high-order 6 bits)
INTBT/INT4 start address (low-order 8 bits)
INT0 start address (high-order 6 bits)
INT0 start address (low-order 8 bits)
INT1 start address (high-order 6 bits)
INT1 start address (low-order 8 bits)
INTCSI0 start address
(high-order 6 bits)
INTCSI0 start address
(low-order 8 bits)
INTT0 start address (high-order 6 bits)
INTT0 start address (low-order 8 bits)
INTTPG start address (high-order 6 bits)
INTTPG start address (low-order 8 bits)
GETI instruction reference table
BR !addr
instruction
branch
address
CALL addr
instruction
branch
address
Branch/call
address specified
in GETI
insturction
CALLF
!faddr
instruction
entry
address
BRCB
!caddr
instruction
branch
address
MBE
RBE
000CH
5000H
4FFFH
4000H
3FFFH
2000H
1FFFH
07FFH
0800H
BR BCDE
BR BCXA
branch address
BRA !addr
instruction
branch address
CALLA !addr
instruction branch
address
BR $addr
instruction
relative
branch address
(–15 to –1,
+2 to +16)
6FFFH
7000H
7F7FH
BRCB !caddr instruction
branch address
BRCB !caddr instruction
branch address
BRCB !caddr instruction
branch address
BRCB !caddr instruction
branch address
BRCB !caddr instruction
branch address
BRCB !caddr instruction
branch address
BRCB !caddr instruction
branch address