參數(shù)資料
型號(hào)： VDP31XXB
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Video Processor Family
中文描述： 視頻處理器系列
文件頁(yè)數(shù)： 24/72頁(yè)
文件大?。?/td> 597K
代理商： VDP31XXB
PRELIMINARY DATA SHEET
VDP 31xxB
24
Micronas
2.9.5. Fast Blank Monitor
The presence of external analog RGB sources can be
detected by means of a fast blank monitor. The status of
the selected fast blank input can be monitored via an I
2
C
bus register. There is a 2 bit information, giving static and
dynamic indication of a fast blank signal. The static bit is
directly reading the fast blank input line, whereas the dy-
namic bit is reading the status of a flip-flop triggered by
the negative edge of the fast blank signal.
With this monitor logic it is possible to detect if there is
an external RGB source active and if it is a full screen in-
sertion or only a box. The monitor logic is connected di-
rectly to the FBLIN1 or FBLIN2 pin. Selection is done via
I
2
C bus register.
FBLIN1
FBLIN2
#
Fast
Blank
Monitor
FBPOL
FBFOH1
FBPRIO
FB
int
Fast
Blank
Selection
FBFOH2
FBMON
FBFOL1
FBFOL2
Fig. 2
–
25:
Fast Blank Selection Logic
#
2.9.6. Half Contrast Control
Insertion of transparent text pages or OSD onto the vid-
eo picture is often difficult to read, especially if the video
contrast is high. The VDP 31xxB allows contrast reduc-
tion of the video background by means of a half contrast
input (HCS pin). This input can be supplied with a fast
switching signal (similar to the fast blank input), typically
defining a rectangular box in which the video picture is
displayed with reduced contrast. The analog RGB inputs
are still displayed with full contrast.
The HCS input is multiplexed with the PORT0 input/out-
put on the same pin, selection is done via I
2
C-bus regis-
ter. If the HCS input is selected, then the port function of
this pin is disabled and writing data into PORT0 will have
no effect. If the HCS input is not selected, the I
2
C-bus
register bits HCSFOH and HCSPOL must be used to
disable the half contrast function.
HCS
HCSEN
HCSFOH
Fig. 2
–
26:
Half Contrast Switch Logic
#
HCS intern
HCSPOL
2.10. IO Port Expander
The VDP 31xxB provides a general purpose IO port to
control and monitor up to seven external signals. The
port direction is programmable for each bit individually.
Via I
2
C bus register it is possible to write or read each
port pin. Because of the relatively low I
2
C bus speed,
only slow or static signals can be handled.
The port signals are multiplexed with other signals to
minimize pin count. PORT0 is multiplexed with the HCS
input signal, PORT1 is multiplexed with the FSY output
signal, PORT[6:2] are multiplexed with the color bus in-
put COLOR[4:0]. The pin configuration is programmable
via I
2
C bus register. All register bits can be read back, the
default configuration after reset is input on PORT[1:0]
and COLOR[4:0] enabled.
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