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參數(shù)資料
| 型號： | VDP31XXB |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video Processor Family |
| 中文描述： | 視頻處理器系列 |
| 文件頁數(shù)： | 29/72頁 |
| 文件大?。?/td> | 597K |
| 代理商： | VDP31XXB |
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PRELIMINARY DATA SHEET
VDP 31xxB
29
Micronas
2.12. Reset Function
Reset of most VDP 31xxB functions is performed by the
RESET pin. When this pin becomes active, all internal
registers and counters are lost. When the RESET pin is
released, the internal reset is still active for 4
μ
s. After
that time, the initialization of all required registers is per-
formed by the internal Fast Processor. During this initial-
ization procedure (see Fig. 2
–
31) it is not possible to ac-
cess the VDP 31xxB via the serial interface (I
2
C).
Access to other ICs via the serial bus is possible during
that time.
The 5 MHz clock divider and the 1 MHz standby clock di-
vider are not affected by reset. The clock source for the
horizontal output generator is switched to the standby
clock during reset.
Reset
Internal
Reset
Initialization
4
μ
s
approx. 60
μ
s
Fig. 2
–
31:
External Reset
2.13. Standby and Power-On
In standby mode the whole signal processing of the VDP
31xxB is disabled and only some basic functions are
working. The standby mode is realized by switching off
the supplies for analog front-end (VSUPF), analog back-
end (VSUPO) and digital circuitry (VSUPD). The stand-
by supply (VSTBY) still has its nominal voltage.
To disable all the analog and digital functions, it is neces-
sary to bring the analog and digital supplies below 0.5 V.
Only this guarantees that all the normal functions are
disabled and the standby current for analog and digital
supply is at its minimum.
When switched off, the negative slope of the supply
voltage VSUPD should not be larger than approximately
0.2 V/
μ
s (see Recommended Operating Conditions).
In the standby mode, all registers and counter values in
the VDP 31xxB are lost, they will be re-initialized via the
internal Fast Processor after analog and digital supplies
are switched on again and the RESET pin is released.
In the standby mode the following functions are still
available (see also 2.11.1.):
–
20.25 MHz crystal oscillator
–
5 MHz clock output (CLK5)
–
horizontal drive output (HOUT)
The clock source for the horizontal output generator is
switched to the standby clock which is derived from the
5 MHz clock. The duty cycle of HOUT is set to 50%.
Protection modes with safety and horizontal flyback pins
are not available.
The VDP 31xxB has clock and voltage supervision cir-
cuits to generate a stable HOUT signal during power-on
and standby. The HOUT signal is disabled until a proper
CLK5 signal (5 MHz clock) is detected. When released,
the HOUT generator runs with the standby clock. Cou-
pling the HOUT generator to the deflection PLL has to
be done by CCU using the EHPLL bit. Fig. 2
–
32 shows
the signals during power-on and standby.
VSTBY
VSUP
D
standby
mode
XTAL
CLK5
Clock
Release
HOUT
Fig. 2
–
32:
Power-On, Standby On/Off
1 μ
s
RESET
Switching the HOUT signal into standby mode can be
done by the CCU via the EHPLL bit or by the internal volt-
age supervision. The voltage supervision activates a
power-down signal when the supply for the digital cir-
cuits (VSUPD) goes below
This power down signal is extended by 50
μ
s after
VSUPD is back again. The power-down signal switches
the clock source for the HOUT generation to the standby
clock and sets the duty cycle to 50%. This is exactly what
the EHPLL bit does.
4.5 V for more than 50ns.
As the clocks from the deflection PLL and the standby
clock are not in phase, the actual phase (High/Low) of
the HOUT signal may be up to one PLL or standby clock
(
1
μ
s) longer than a regular one when the clock source
is changed.
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