參數(shù)資料
型號: VS6724
廠商: 意法半導體
英文描述: 2 Megapixel single-chip camera module
中文描述: 兩百萬像素的單芯片相機模塊
文件頁數(shù): 28/118頁
文件大?。?/td> 1200K
代理商: VS6724
Functional description
VS6724
28/118
When ViewLive is enabled the output data switches between
PipeContext0
and
PipeContext
1
on each alternate frame.
Figure 12.
ViewLive frame output format
2.9
Output formats
2.9.1
Image size
An output frame consists of a number of active lines and a number of interframe lines. Each
line consists of embedded line codes (if selected), active pixel data and interline blank data.
Note that by default the interline blanking data is notqualified by the PCLK and therefore is
not captured by the host system.
The image size can be either the full output from the sensor, depending on sensor mode, or
a scaled output, The output image size can be chosen from one of 9 pre-selected sizes or a
manual image size can be used.
The VS6724 supports the following data formats:
JPEG (4:2:2, 4:2:0)
YCbCr 4:2:2
YCbCr 4:0:0
RGB565
RGB444 (encapsulated as 565)
RGB444 (zero padded)
Bayer 10-bit
Bayer 8-bit
The required data format is selected using the bdataFomat control found in the pipe context
registers. The various options available for each format are controlled using the bRgbsetup
and bYCbCrSetup registers found in the
Dither control
registers.
Interframe Blanking
Active Video
Pipe context0
Interline
Blanking
Interline
Blanking
Interframe Blanking
Active Video
Pipe context1
Frame output
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