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參數(shù)資料
| 型號： | VS6724 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 Megapixel single-chip camera module |
| 中文描述： | 兩百萬像素的單芯片相機(jī)模塊 |
| 文件頁數(shù)： | 41/118頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | VS6724 |
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VS6724
Host communication - I2C control interface
41/118
3
Host communication - I2C control interface
The interface used on the VS6724 is a subset of the I2C standard. Higher level protocol
adaptations have been made to allow for greater addressing flexibility. This extended
interface is known as the V2W interface.
3.1
Protocol
A message contains two or more bytes of data preceded by a START (S) condition and
followed by either a STOP (P) or a repeated START (Sr) condition followed by another
message.
STOP and START conditions can only be generated by a V2W master.
After every byte transferred the receiving device must output an acknowledge bit which tells
the transmitter if the data byte has been successfully received or not.
The first byte of the message is called the device address byte and contains the 7-bit
address of the V2W slave to be addressed plus a read/write bit which defines the direction
of the data flow between the master and the slave.
The meaning of the data bytes that follow device address changes depending whether the
master is writing to or reading from the slave.
Figure 25. Write message
For the master writing to the slave the device address byte is followed by 2 bytes which
specify the 16-bit internal location (index) for the data write. The next byte of data contains
the value to be written to that register index. If multiple data bytes are written then the
internal register index is automatically incremented after each byte of data transferred. The
master can send data bytes continuously to the slave until the slave fails to provide an
acknowledge or the master terminates the write communication with a STOP condition or
sends a repeated START (Sr).
Figure 26. Read message
For the master reading from the slave the device address is followed by the contents of last
register index that the previous read or write message accessed. If multiple data bytes are
read then the internal register index is automatically incremented after each byte of data
‘0’ (Write)
S
DEV ADDR R/W A
2 Index Bytes
DATA
P
A/A
DATA
A
N Data Byte
A
DATA
From Master to Slave
From Slave to Master
‘1’ (Read)
S
DEV ADDR R/W A
DATA
P
A
DATA
A
1 or more Data Byte
From Master to Slave
From Slave to Master
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| VS6724P0FY | 制造商:STMicroelectronics 功能描述: |
| VS6724Q0FB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Megapixel single-chip camera module |
| VS6725 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 megapixel single-chip camera module |
| VS6725Q045 | 制造商:STMicroelectronics 功能描述: |
| VS6725XQ045/TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 megapixel single-chip camera module |
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