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參數(shù)資料
| 型號(hào)： | VS6724 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 Megapixel single-chip camera module |
| 中文描述： | 兩百萬(wàn)像素的單芯片相機(jī)模塊 |
| 文件頁(yè)數(shù)： | 50/118頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | VS6724 |
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Programming model and register description
VS6724
50/118
4
Programming model and register description
4.1
Programming model
The VS6724 addressable register/memory space is configured as shown below. It consists
of four principal areas each of which provides a different function:
User Interface
: this area starting from address zero provides the user interface. Register
reads and writes to this block are passed through the internal micro and processed. All
operational control of the device by the host should be performed through these user
interface locations.Many of these registers are detailed in
Section 4.2: Register description
.
Registers not listed in this datasheet should be considered as reserved or read-only and
should NOT be written to, as this may cause unpredictable results.
Hardware registers
: provides direct access to hardware registers associated with each
functional block of the device. In normal operation, these registers will be accessed under
the control of the micro. i.e. they should never be accessed by the host system. However,
they may be directly accessed by the host for debug and test purposes.
XDATA RAM
: provides temporary variable storage for the on-board micro.
Patch RAM
: provides memory space to download firmware patches and modify device
operation. This provides a software update mechanism without the need for a new program
ROM.
Figure 39.
FFFF
System / Host view of VS6724 memory
0000
8000
C000
D800
8FFF
9000
9FFF
USER INTERFACE
4K MCU XDATA RAM
4K MCU PATCH RAM
HARDWARE REGISTERS
User Interface
Hardware Registers
XDATA/Patch RAM
Blank space
LEGEND
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