參數(shù)資料
型號(hào)： VT86C100A
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI FAST ETHERNET CONTROLLER
中文描述： PCI快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 10/32頁(yè)
文件大小： 349K
代理商： VT86C100A
VIA Technologies, Inc.
Preliminary VT86C100A
3.
EEPROM Interface and Programming
VT86C100A uses an 93C46 to store configuration data and Ethernet address.
3
.1.
EEPROM Contents
D15
D0
3FH
.
.
.
.
.
.
10H
0FH
0EH
0DH
0CH
0BH
0AH
09H
08H
07H
06H
05H
04H
03H
02H
01H
00H
Reserved for 93C46
.
.
.
.
.
.
.
73H
CFG_D
CFG_B
BCR1
MAX_LAT
Reserved
KEY5
KEY3
KEY1
Reserved
SUBVID1
SUBSID1
Reserved
Ethernet Address 5
Ethernet Address 3
Ethernet Address 1
Reserved for 93C46
.
.
.
.
.
.
.
73H
CFG_C
CFG_A
BCR0
MIN_GNT
Reserved
KEY5
KEY2
KEY0
Reserved
SUBVID0
SUBSID0
Reserved
Ethernet Address 4
Ethernet Address 2
Ethernet Address 0
Note 1.
The word on location 03H is optional to user's application requirement.
Note 2.
Programming 73H into the upper address is required to protect the Ethernet address from being destroyed accidentally
Note 3.
The word on location 04H, 05H is sub-System ID, sub-Vendor ID in PCI specification 2.1.
3.2. D
IRECT
P
ROGRAMMING OF
EEPROM
The VT86C100A features a easy way to program external EEPROM in-situ. When the RESET is active and if
the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current
EEPROM has not been programmed yet. This will allow the VT86C100A to enter Direct Programming mode
if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by writing to
the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS, SK(MD2), and
DI(MD1) outputs respectively. These outputs will be latched so the user can generate a clock on SK by
repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the EEPROM signals as per
the 93C46 data sheet.
To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as
described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data
Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the
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