參數(shù)資料
型號: VT86C100A
廠商: Electronic Theatre Controls, Inc.
英文描述: PCI FAST ETHERNET CONTROLLER
中文描述: PCI快速以太網(wǎng)控制器
文件頁數(shù): 22/32頁
文件大小: 349K
代理商: VT86C100A
VIA Technologies, Inc.
Preliminary VT86C100A
1.1 Configure Register Layout
Configuration Register A (0x78)
0
GPIO2OE
MD3
GPIO2OE
: Output enable of GPIO2 pin
GPIO2O :
Output to GPIO2 pin
GPIO2I :
GPIO2 input status
AUTOOPT :
enable receive event auto transmit descriptor polling
MMIEN :
Memory mapped IO enable, accept memory command
JUMPER :
Jumper mode to select PHY and operation mode
EELOAD :
Enable EEPROM embedded and direct programming
GPIO2
Configuration Register B (0x79)
0
LATMEN
n/a
LATMEN:
Latency timer effect enable
MRWAIT :
Master read insert one wait state 2-2-2-2
MWWAIT:
Master write insert one wait state 2-2-2-2
RXARBIT :
the receiving FIFO DMA will be interleave to transmitting
FIFO DMA after 32 double words transaction.
TXARBIT
: the transmitting FIFO DMA will be interleave to receiving
FIFO DMA after 32 double words transaction.
MRDM :
Memory read multiple capable
TPACEN :
Tx descriptor pacing algorithm enable
QPKTDIS :
disable transmit frame queuing.
4
TXARBIT
n/a
7
QPKTDIS
n/a
Configuration Register C (0x7A)
Bit
Symbol
0-2
BPS0-
BPS3
Jumper
n/a
Function
Boot PROM Select:
Select size at which boot PROM begins and the
size
Bit2
Bit1
Bit0
Size
0
0
0
No Boot PROM
0
0
1
8K
0
1
0
16K
0
1
1
32K
1
X X
64K
BTSEL :
Bootrom timing select
DLYEN
: Delay transaction while memory read Bootrom
BROPT
: set Bootrom address line above Bootrom size selected to logic
1
for small size Bootrom
Configuration Register D (0x7B)
0
BAKOPT
n/a
BAKOPT :
Back-off algorithm optional
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