參數(shù)資料
型號(hào)： VT86C100A
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI FAST ETHERNET CONTROLLER
中文描述： PCI快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 6/32頁(yè)
文件大?。?/td> 349K
代理商： VT86C100A
VIA Technologies, Inc.
Preliminary VT86C100A
P
IN
D
ESCRIPTIONS
No.
Name
Type
Description
PCI Bus Interface
121-
124,127-
128,1-
2,5,7-
9,11-
14,27-
32,35-
36,38,39-
40,42-46
115
AD31-0
I/O
Address/Data are multiplexed on the same PCI pins. A bus transaction
consists of an address phase followed by one or more data phases. The
address phase is the clock cycle in which FRAME# is asserted. Write
data is stable and valid when IRDYB is asserted and read data is stable
and valid when TRDYB is asserted.
PCICLK
I
PCICLK provides timing for all transactions on PCI and is an input pin
to every PCI device.
INTA# is an asynchronous signal which is used to request an interrupt
When PCIRST# is asserted low, the VT86C100A chip performs an
internal system hardware reset. PCIRST# may be asynchronous to CLK
when asserted or deasserted. It is recommended that the deassertion be
synchronous to guarantee clean and bounce free edge.
Bus Command/Byte Enables are multiplexed on the same PCI pins.
During the address phase of a transaction, CBE3-0B define the Bus
Command. Burring the data phase, CBE3-0B are used as Byte Enables.
The Byte Enables define which physical byte lanes carry meaningful
data. CBE0B applies to byte 0 and CBE3B applies to byte 3.
Used as a chip select during PCI configuration cycle.
Cycle Frame is driven by the current master to indicate the beginning
and duration of an access. FRAME# is asserted to indicate a bus
transaction is beginning. While FRAME# is asserted, data transfers
continue. When FRAME# is deasserted, the transaction is in the final
data phase.
Initiator Ready indicates the initiating agent's ability to complete the
current data phase of the transaction. IRDY# is used in conjunction with
TRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a write, IRDY# indicates that valid data is
present on AD31-0. During a read, it indicates the master is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.
Target Ready indicates the target's agent's ability to complete the current
data phase of the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is completed on any clock when both IRDY# and
TRDY# are asserted. During a read, TRDY# indicates that valid data is
present on AD31-0. During a write, it indicates the target is prepared to
accept data. Wait cycles are inserted until both IRDY# and TRDY# are
asserted simultaneously.
Device Select, when actively driven, indicates the driving device has
decoded its address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been selected.
VT86C100A drives STOP# to disconnect further traction.
113
114
INTA#
PCIRST#
OD
I
3,16,26,37
CBE#[3:0]
I
4
17
IDSEL
FRAME#
I
I/O
18
IRDY#
I/O
19
TRDY#
I/O
20
DEVSEL#
I/O
21
STOP#
I/O
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