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參數資料
| 型號： | VT86C100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI FAST ETHERNET CONTROLLER |
| 中文描述： | PCI快速以太網控制器 |
| 文件頁數： | 7/32頁 |
| 文件大?。?/td> | 349K |
| 代理商： | VT86C100A |
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VIA Technologies, Inc.
Preliminary VT86C100A
25
PAR
T/S
Parity is even parity across AD31-0 and CBE3-0B. PAR is stable and
valid one clock after the address phase. For data phases PAR is stable
and valid one clock after either IRDY# is asserted on a write transaction
or TRDY# is asserted on a read transaction.
Bus grant asserts to indicate to the VT86C100A that access to the bus is
granted.
Bus request is asserted by the bus master indicate to the bus arbiter that
it wants to use the bus.
Parity error asserts when a data parity error is detected
Power management event interrupt
When PCIRST# is asserted low, the VT86C100A chip performs an
internal system hardware reset. Then HDRST is asserted high for
external device reset signal like PHY device.
118
GNT#
I
119
REQ#
O
23
120
111
PERR#
PME#
HDRST
I/O
O
O
Network Interface
91
90
92-95
MCOL
MCRS
MTXD[3-0]
I
I
Collision detect when the external PHY device
Carrier sense is asserted by the external PHY when the media is active
MII 4 parallel transmit data lines. This data be synchronized to assertion
by the MTXC signal
Transmit enable signals that the transmit is active in the MII port to an
external PHY device
MII transmit clock supports the 25mhz or 2.5mhz transmit clock
supplied by the external PMD device. This clock should always be
active.
MII receive error asserts when a data decoding error is detected by
external PHY device.
MII receive clock supports the 25mhz or 2.5mhz clock. This clock is
recovered by the PHY.
MII data valid
Four parallel receive data lines. This data be driven from external PHY
be synchronized with MRXC signal.
MII management data clock be soured by VT86C100A MDC bit
(MIIR:0) to the external PHY devices as timing reference for the
MDIO signal.
MII management data input/output, read from MDI bit (MIIR:1) or
written from MDO bit (MIIR:2)
GPIO
O
96
MTXEN
O
99
MTXC
I
100
MERR
I
101
MRXC
I
102
MRXDV
MRXD[0-3]
I
I
103-106
109
MDC
O
110
MDIO
I/O
112
GPIO
I/O
External Memory Support & General purpose I/O support
49
EECS
O
EEPROM Chip Select: Chip select signal for the external EEPROM
when a EEPROM is used to provide the configuration data and
Ethernet Address. A 100K pull-up resistor is connected.
Boot PROM Read: Read the Boot ROM on the memory support data
bus.
Bootrom data 0
Serial ROM Data output
Bootrom data 1
Serial ROM Data input
Bootrom data 2
Serial ROM Clock signal
Bootrom Data [3-7] :
50
BPRD#
O
51
MD0/
EEDO
MD1/
EEDI
I/O
52
O/O
53
MD2/ EECLK
O/O
54-55,58-
60
MD3-7
I/O
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