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參數(shù)資料
| 型號： | W230 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 174K |
| 代理商： | W230 |
W230
Document #: 38-07224 Rev. *A
Page 10 of 15
AC Electrical Characteristics
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5%, f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum is disabled.
CPU Clock Outputs (CPUT0, CPUC0, CPUT_CS)
[8]
Notes:
5.
6.
X1 input threshold voltage (typical) is V
/2.
The W230 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Refer to
Figure 5
for K7 operation clock driver test circuit.
7.
8.
Crystal Oscillator
V
TH
C
LOAD
X1 Input Threshold Voltage
[5]
Load Capacitance, Imposed on
External Crystal
[6]
X1 Input Capacitance
[7]
Pin Capacitance/Inductance
C
IN
Input Pin Capacitance
C
OUT
Output Pin Capacitance
L
IN
Input Pin Inductance
V
DDQ3
= 3.3V
1.65
14
V
pF
C
IN,X1
Pin X2 unconnected
28
pF
Except X1 and X2
5
6
7
pF
pF
nH
DC Electrical Characteristics:
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Parameter
t
R
t
F
t
D
t
JC
f
ST
Description
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle to Cycle
Frequency Stabilization
from Power-up (cold
start)
Test Condition/Comments
CPU = 100 MHz
Min.
Typ.
1.0
1.0
50
250
3
CPU = 133 MHz
Min.
Typ.
1.0
1.0
50
250
Unit
V/ns
V/ns
%
ps
ms
Max.
Max.
Measured at 50% point
Assumes full supply voltage reached
within 1 ms from power-up. Short
cycles exist prior to frequency
stabilization.
V
O
= V
X
3
Z
o
AC Output Impedance
50
50
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