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參數(shù)資料
| 型號： | W230 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 174K |
| 代理商： | W230 |
W230
Document #: 38-07224 Rev. *A
Page 5 of 15
Serial Data Interface
The W230 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W230 initializes
with default register settings, therefore the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions.
Table 3
summarizes the control functions of
the serial data interface.
Operation
Data is written to the W230 in eleven bytes of eight bits each.
Bytes are written in the order shown in
Table 4
.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Description
Common Application
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change un-
der normal system operation.
For EMI reduction.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
Spread Spectrum
Enabling
Output Three-state
(Reserved)
Enables or disables spread spectrum clocking.
Puts clock output into a high impedance state.
Reserved function for future device revision or pro-
duction device testing.
Production PCB testing.
No user application. Register bit must be writ-
ten as 0.
Table 4. Byte Writing Sequence
Byte Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W230 to accept the bits in Data Bytes 0
–
6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W230 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W230, therefore bit values are ignored (
“
don
’
t care
”
). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Unused by the W230, therefore bit values are ignored (
“
don
’
t care
”
). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
The data bits in Data Bytes 0
–
7 set internal W230 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to
Table 5
, Data Byte Serial Configuration Map.
2
Command
Code
Don
’
t Care
3
Byte Count
Don
’
t Care
4
5
6
7
8
9
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Refer to
Table 5
10
11
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| W230-03 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Spread Spectrum FTG for VIA K7 Chipset |
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| W230CR3.80HR | 制造商:Calmark 功能描述: |
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