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參數(shù)資料
| 型號： | W230 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 174K |
| 代理商： | W230 |
W230
Document #: 38-07224 Rev. *A
Page 12 of 15
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
f
D
Deviation from 24 MHz
m/n
PLL Ratio
t
R
Output Rise Edge Rate
t
F
Output Fall Edge Rate
t
D
Duty Cycle
f
ST
Frequency Stabilization
from Power-up (cold start)
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(24.004
–
24)/24
(14.31818 MHz x 57/34 = 24.004 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
24.004
+167
57/34
Max.
Unit
MHz
ppm
0.5
0.5
45
2
2
V/ns
V/ns
%
ms
55
3
Z
o
AC Output Impedance
40
Clock Chip
CPU
Driver
1.5V
R1
68
Z0 = 52
T2
”
Z0 = 52
Length = 5
”
T1
R8
47
CPUCLK_T
VDD
3.3
+
–
V1
Z0 = 52
T5
”
Z0 = 52
Length = 5
”
T4
R9
47
20p
20p
CPUCLK_C
1.5V
R3
68
Figure 5. K7 Open Drain Clock Driver Test Circuit
Ordering Information
Ordering Code
W230
Package
Name
H
Package Type
48-pin SSOP (300 mils)
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