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參數(shù)資料
| 型號： | W230 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 174K |
| 代理商： | W230 |
W230
Document #: 38-07224 Rev. *A
Page 6 of 15
Writing Data Bytes
Each bit in the data bytes controls a particular device function
except for the
“
reserved
”
bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7.
Table 5
gives the bit formats for registers located in Data
Bytes 0
–
7.
Table 6
details additional frequency selections that are avail-
able through the serial data interface.
Table 5. Data Bytes 0
–
7 Serial Configuration Map
Affected Pin
Pin No.
Pin Name
Data Byte 0
7
--
6
--
5
--
4
--
3
--
Bit(s)
Control Function
Bit Control
Default
0
1
--
--
--
--
--
(Reserved)
SEL_2
SEL_1
SEL_0
Hardware/Software Frequency
Select
SEL_4
SEL_3
--
--
0
0
0
0
0
See
Table 6
See
Table 6
See
Table 6
Hardware
Software
2
1
0
--
--
--
--
--
--
See
Table 6
See
Table 6
1
0
0
Normal
Three-stated
Data Byte 1
7
6
5
4
3
2
1
0
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved) Write to
‘
1
’
(Reserved) Write to
‘
1
’
(Reserved) Write to
‘
1
’
(Reserved) Write to
‘
1
’
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
1
1
1
1
--
7
--
13
12
11
10
8
--
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
0
1
0
1
1
1
1
1
PCI0
--
PCI5
PCI4
PCI3
PCI2
PCI1
Low
--
Low
Low
Low
Low
Low
Active
--
Active
Active
Active
Active
Active
--
--
--
(Reserved)
SEL_48MHz as the output fre-
quency for 24_48MHz
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
--
--
0
0
SEL_48MHz
24-MHz
48-MHz
5
4
3
2
26
25
--
48MHz
24_48MHz
--
SDRAM8:11
Low
Low
--
Low
Active
Active
--
Active
1
1
0
1
21, 20,
18, 17
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