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參數(shù)資料
| 型號： | W230 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 174K |
| 代理商： | W230 |
W230
Document #: 38-07224 Rev. *A
Page 2 of 15
Pin Definitions
Pin Name
CPUT0,
CPUC0,
CPUT_CS
PCI2:5
Pin No.
43, 44, 46
Pin Type
O
(open-
drain)
O
Pin Description
CPU Clock Output 0:
CPUT0 and CPUC0 are the
differential CPU clock outputs
for the K7 processor. CPUT_CS is the open-drain clock output for the chipset. It
has the same phase relationship as CPUT0.
PCI Clock Outputs 2 through 5:
These four PCI clock outputs are controlled by
the PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial
input interface, see
Tables
2
and
6
for details. Output voltage swing is controlled
by voltage applied to VDDQ3.
Fixed PCI Clock Output/Frequency Select 1:
As an output, frequency is set by
FS0:3 inputs or through serial input interface. This output is controlled by the
PWRDWN# input. This pin also serves as a power-on strap option to determine
device operating frequency as described in
Table 2
.
Fixed PCI Clock Output/Mode:
As an output, frequency is set by the FS0:3 inputs
or through serial input interface, see
Tables
2
and
6
. This output is controlled by
the PWRDWN# input. This pin also serves as a power-on strap option to determine
the function of pin 2, see
Table 1
for details.
PWRDWN# Input:
LVTTL-compatible input that places the device in power-down
mode when held LOW. In power-down mode,CPUC0 will be three-stated and all
the other output clocks will be driven LOW.
48-MHz Output/Frequency Select 2:
48 MHz is provided in normal operation. In
standard PC systems, this output can be used as the reference for the Universal
Serial Bus host controller. This pin also serves as a power on strap option to
determine device operating frequency as described in
Table 2
.
24/48-MHz Output/Frequency Select 3:
In standard PC systems, this output can
be used as the clock input for a Super I/O chip. The output frequency is controlled
by Configuration Byte 3 bit[6]. The default output frequency is 48 MHz. This pin
also serves as a power-on strap option to determine device operating frequency
as described in
Table 2
.
Reference Clock Output 1/Frequency Select 2:
3.3V 14.318-MHz output clock.
This pin also serves as a power-on strap option to determine device operating
frequency as described in
Table 2
. Upon power-up, FS0 input will be latched which
will set clock frequencies as described in
Table 2
.
Reference Clock Output 0 or CPU_STOP# Input Pin:
Function is determined
by the MODE pin. When CPU_STOP# input is asserted LOW, it will drive CPUT0
and CPUT_CS to logic 0, and it will three-state CPUC0. When this pin is configured
as an output, this pin becomes a 3.3V 14.318-MHz output clock.
Buffered Input Pin:
The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:12).
Buffered Outputs:
These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deac-
tivated when PWRDWN# input is set LOW.
10, 11, 12, 13
PCI1/FS1
8
I/O
PCI0/MODE
7
I/O
PWRDWN#
41
I
48MHz/FS2
26
I/O
24_48MHz/
FS3
25
I/O
REF1/FS0
48
I/O
REF0/
CPU_STOP#
2
I/O
SDRAMIN
15
I
SDRAM0:12
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17, 40
24
23
4
O
SCLK
SDATA
X1
I
Clock pin for I
2
C circuitry.
Data pin for I
2
C circuitry.
Crystal Connection or External Reference Frequency Input:
This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection:
An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection:
Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24/48-MHz output. Connect
to 3.3V supply
Ground Connections:
Connect all ground pins to the common system ground
plane.
I/O
I
X2
5
I
VDDQ3
1, 6, 14, 19,
27, 30, 36, 42
P
GND
3, 9, 16, 22,
33, 39, 45, 47
G
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