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參數(shù)資料
| 型號： | W234 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 160K |
| 代理商： | W234 |
W234
Document #: 38-07232 Rev. *B
Page 10 of 14
Notes:
2.
3.
4.
5.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Refclk jitter measured at V
(nom)/2.
If input modulation is used: input modulation is allowed but not required.
The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
Capacitance measured at Freq = 1 MHz, DC bias = 0.9V and V
AC
< 100 mV.
6.
Table 12. Operating Conditions
[2]
Parameter
V
DD
Supply Voltage
T
A
Ambient Operating Temperature
t
CYCLE,IN
Refclk Input Cycle Time
t
J,IN
DC
IN
Input Duty Cycle over 10,000 Cycles
FM
IN
Input Frequency of Modulation
PM
IN[4]
Modulation Index for Triangular Modulation
Modulation Index for Non-Triangular Modulation
t
CYCLE,PD
Phase Detector Input Cycle Time at PCLKM & SYNCLKN
t
ERR,INIT
Initial Phase error at Phase Detector Inputs
DC
IN,PD
Phase Detector Input Duty Cycle over 10,000 Cycles
t
I,SR
Input Slew Rate (measured at 20%-80% of input voltage) for
PCLKM, SYNCLKN, and REFCLK
C
IN,PD
C
IN,PD
C
IN,CMOS
Input Capacitance at CMOS pins (excluding PCLKM, SYNCLKN,
and REFCLK)
[6]
V
IL
Input (CMOS) Signal Low Voltage
V
IH
Input (CMOS) Signal High Voltage
V
IL,R
Refclk Input Low Voltage
V
IH,R
Refclk Input High Voltage
V
IL,PD
Input Signal Low Voltage for PD Inputs and STOP#
V
IH,PD
Input Signal High Voltage for PD Inputs and STOP#
V
DDIR
Input Supply Reference for REFCLK
V
DDIPD
Input Supply Reference for PD Inputs
Description
Min.
3.135
0
10
–
40
30
–
–
30
–
0.5
25
1
Max.
3.465
70
40
250
60
33
0.6
0.5
[5]
100
0.5
75
4
Unit
V
°
C
ns
ps
%t
CYCLE
kHz
%
%
ns
t
CYCLE,PD
t
CYCLE,PD
V/ns
Input Cycle-to-Cycle Jitter
[3]
Input Capacitance at PCLKM, SYNCLKN, and REFCLK
[6]
Input Capacitance matching at PCLKM and SYNCLKN
[6]
–
–
–
7
pF
pF
pF
0.5
10
–
0.3
-
0.3
–
0.3
–
3.465
2.625
VDD
VDD
V
DDIR
V
DDIR
V
DDIPD
V
DDIPD
V
V
0.7
-
0.7
–
0.7
1.235
1.235
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