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參數(shù)資料
| 型號： | W234 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 160K |
| 代理商： | W234 |
W234
Document #: 38-07232 Rev. *B
Page 5 of 14
Table 4
shows the logic for selecting the Power-Down mode,
using the PWR_DWN# input signal. PWR_DWN# is active
LOW (enabled when 0). When PWR_DWN# is disabled, the
DRCG is in its normal mode. When PWR_DWN# is enabled,
the DRCG is put into a powered-off state, and the CLK and
CLK# outputs are three-stated.
Table of Frequencies and Gear Ratios
Table 5
shows several supported Pclk and Busclk frequencies,
the corresponding A and B dividers required in the DRCG PLL,
and the corresponding M and N dividers in the gear ratio logic.
The column Ratio gives the Gear Ratio as defined Pclk/Synclk
(same as M and N). The column F@PD gives the divided down
frequency (in MHz) at the Phase Detector (
φ
D
), where
F@PD = PCLK/M = SYNCLK/N.
State Transitions
The clock source has three fundamental operating states.
Figure 4
shows the state diagram with each transition labelled
A through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PWR_DWN#
and STOP#.
In Power-Down mode, the clock source is powered down with
the control signal, PWR_DWN#, equal to 0. The control sig-
nals S0, S1 and S2 must be stable before power is applied to
the device, and can only be changed in Power-Down mode
(PWR_DWN#=0). The reference inputs, VDDIR and VDDIPD,
may remain on or may be grounded during the Power-Down
mode.
The control signals MULT0, MULT1, and MULT2 can be used
in two ways. If they are changed during Power-Down mode,
then the Power-Down transition timings determine the settling
time of the DRCG. However, the MULT0, MULT1, and MULT2
control signals can also be changed during Normal mode.
When the MULT control signals are
“
hot swapped
”
in this man-
ner, the MULT transition timings determine the settling time of
the DRCG.
Table 3. Bypass and Test Mode Selection
Mode
S0
S1
S2
By Pclk
(int.)
CLK
CLK#
Normal
0
0
0
Gnd
PAClk
PAClk#
Bypass
1
0
0
PLLClk
PLLClk
PLLClk#
Test
1
1
0
RefClk
RefClk
RefClk#
Vendor Test
A
0
0
1
-
-
-
Vendor Test
B
1
0
1
-
-
-
Reserved
1
1
1
-
-
-
Output Test
(OE)
0
1
X
-
Hi-Z
RefClk#
Table 4. PWR_DWN# Mode Selection
Mode
PWR_DWN#
Normal
Power-Down
CLK
PAClk
GND
CLK#
PAClk#
GND
1
0
Table 5. Frequencies, Dividers, and Gear Ratios
Pclk
Refclk
67
33
100
50
100
50
133
67
133
67
Busclk
267
300
400
267
400
Synclk
67
75
100
67
100
A
8
6
8
4
6
B
1
1
1
1
1
M
2
8
4
4
8
N
2
6
4
2
6
Ratio
1.0
1.33
1.0
2.0
1.33
F@PD
33
12.5
25
33
16.7
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